Serial memory controller helps next-gen CPUs perform AI, ML
Designed to address the memory bandwidth needs of increasing core counts in CPUs and SoCs, the SMC 1000 8x25G enables CPUs and other compute-centric SoCs to use four times the memory channels of parallel attached DDR4 DRAM within the same package footprint. The device, says the company, enables higher memory bandwidth and media independence for high performance computing (HPC), big data, artificial intelligence (AI) and machine learning (ML) compute-intensive applications with ultra-low latency.
“Microchip is excited to introduce the industry’s first serial memory controller device to the market,” says Pete Hazen, vice president of Microchip’s Data Center Solutions business unit. “New memory interface technologies such as Open Memory Interface (OMI) enable a broad range of SoC applications to support the increasing memory requirements of high-performance data center applications. Microchip’s entrance into the memory infrastructure market underscores our commitment to improving performance and efficiency in the data center.”
The SMC 1000 8x25G interfaces to the CPU via 8-bit Open Memory Interface (OMI)-compliant 25-Gbps lanes and bridges to memory via a 72-bit DDR4 3200 interface. The result is a significant reduction in the required number of host CPU or SoC pins per DDR4 memory channel, allowing for more memory channels and increasing the memory bandwidth available.
A CPU or SoC with OMI support can use a broad set of media types with different cost, power, and performance metrics without having to integrate a unique memory controller for each type. In contrast, CPU and SoC memory interfaces today are typically locked to specific DDR interface protocols, such as DDR4, at specific interface rates. The SMC 1000 8x25G is the first memory infrastructure product in the company’s portfolio that enables the media-independent OMI interface.
Data center application workloads require OMI-based DDIMM memory products to deliver the same high-performance bandwidth and low latency results of today’s parallel-DDR-based memory products. The SMC 1000 8x25G’s low-latency design, says the company, delivers less than four nanoseconds incremental latency over a traditional integrated DDR controller with LRDIMM, resulting in OMI-based DDIMM products having virtually identical bandwidth and latency performance to comparable LRDIMM products.
SMART Modular, Micron and Samsung Electronics are building multiple pin-efficient 84-pin Differential Dual-Inline Memory Modules (DDIMM) with capacities ranging from 16 GB to 256 GB, conforming to the draft JEDEC DDR5 standard DDIMM form factor. These DDIMMs will leverage the SMC 1000 8x25G and will seamlessly plug into any OMI-compliant 25 Gbps interface.
The SMC 1000 comes with design-in collateral and ChipLink diagnostic tools that provide extensive debug, diagnostics, configuration and analysts tools with an intuitive GUI. The device is sampling now.
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