Serial memory controller targets data center computing
The SMC 1000 8x25G enables CPUs and other compute-centric SoCs to use four times the memory channels of parallel attached DDR4 DRAM within the same package footprint. Microchip’s serial memory controllers deliver higher memory bandwidth and media independence to these compute-intensive platforms with ultra-low latency.
As the number of processing cores within CPUs has risen, the average memory bandwidth available to each processing core has decreased because CPU and SoC devices cannot scale the number of parallel DDR interfaces on a single chip to meet the needs of the increasing core count. The SMC 1000 8x25G interfaces to the CPU via 8-bit Open Memory Interface (OMI)-compliant 25 Gbps lanes and bridges to memory via a 72-bit DDR4 3200 interface. The result is a significant reduction in the required number of host CPU or SoC pins per DDR4 memory channel, allowing for more memory channels and increasing the memory bandwidth available.
The SMC 1000 8x25G is the first memory infrastructure product in Microchip’s portfolio that enables the media-independent OMI interface. The chip features an innovative low latency design that delivers less than 4 ns incremental latency to the first DRAM data access and identical subsequent data access performance. This results in OMI-based DDIMM products having virtually identical bandwidth and latency performance to comparable LRDIMM products.
SMART Modular, Micron and Samsung Electronics are building multiple pin-efficient 84-pin DDR4 Differential Dual-Inline Memory Modules (DDIMM) with capacities ranging from 16 GB to 256 GB. These DDIMMs will leverage the SMC 1000 8x25G and will seamlessly plug into any OMI-compliant 25 Gbps interface.
To support customers building systems that are compliant with the OMI standard, the SMC 1000 comes with design-in collateral and ChipLink diagnostic tools that provide extensive debug, diagnostics, configuration and analysts tools with an intuitive GUI.
Microchip Technology – www.microchip.com
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