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SGVC 3D NAND architecture could easily reach 6Gb/mm2 says Macronix

SGVC 3D NAND architecture could easily reach 6Gb/mm2 says Macronix

Technology News |
By eeNews Europe



The SGVC technology departs from the typical gate-all-around (GAA) devices proposed by competition for ultra-high-density 3D NAND memories. GAA devices are typically arranged vertically, which makes their critical dimensions more difficult control at high aspect ratios, claims Macronix who first presented the SGVC concept two years ago. Instead, the SGVC 3D NAND makes use of arrays of vertically arranged single-gate, flat-cell thin film transistors with an ultra-thin body, which aren’t as sensitive to critical dimensions variation as GAA devices.

Schematic diagram illustrating the advantages of the SGVC flat-channel device over GAA devices. Oxide-nitride-oxide (ONO) layers and polysilicon keep the channel flat even with a non-ideal vertical etching, giving much greater tolerance to 3D etching performance.

The company’s presentation, “A 128Gb (MLC)/192Gb (TLC) Single-Gate Vertical Channel (SGVC) Architecture 3D NAND using only 16 Layers with Robust Read Disturb, Long-Retention and Excellent Scaling Capability” compares its SGVC architecture’s merits with other 3D NAND architectures, succeeding in doubling the density of its array design and achieving memory densities on par with competing designs requiring 48 layers.


Cross-sectional views in the channel length (a) and
width (b) directions, respectively.

The 16-layer test chip realized exhibited a memory density (at die level) of about 1.6Gb/mm2 (in a multi-layer cell configuration) or about 2.4Gb/mm2 in a triple-level cell configuration (or 3.4Gb/mm2 for the memory array alone) and successfully withstood a 120 million read endurance test without the need to refresh or wear-levelling, making it suitable for read-intensive applications such as game-grade memory.

Now the company hints that building a SGVC 3D NAND with 48 layers could yield a memory density of 6Gb/mm2 for 1Tb single-chip devices, slashing the overall bit cost by orders of magnitude to under 0.04 USD/GByte. This is to be compared with today’s bit cost around 0.12 to 0.2 USD/GByte.

The presenters note that because the SGVC 3D NAND architecture involves a simpler array process (no gate replacement, no complex bottom source connection), it is pitch scalable without physical limitations.

Macronix International – www.macronix.com

Related articles:

IMEC reports nanowire FET in ‘vertical’ SRAM

Intel outlines 3D NAND transition

Leti’s 5nm node to stack Si nanowires

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