Siemens automates 2.5D and 3D IC design-for-test

Siemens automates 2.5D and 3D IC design-for-test

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By Nick Flaherty

Siemens Digital Industries Software has developed an automated design-for-test tool flow for 2.D chiplet and 3D stacked chip designs.

The Tessent Multi-die software is intended to help designers simplify critical design-for-test (DFT) tasks. The company recently teamed up with foundry UMC on the production of such designs.

2.5D and 3D designs can present significant challenges for IC test, since most legacy IC test approaches are based on conventional two-dimensional processes.

To address these challenges, the Tessent Multi-die software works with Siemens’ Tessent TestKompress Streaming Scan Network software and Tessent IJTAG software. These optimize DFT test resources for each block without concern for impacts to the rest of the design, streamlining DFT planning and implementation for the 2.5D and 3D IC era.

It supports integration of flexible parallel port (FPP) technology by using packetized data from the TestKompress Streaming Scan Network software. Introduced two years ago, this decouples core-level DFT requirements from the chip-level test delivery resources and enables a bottom-up DFT flow that can simplify DFT planning and implementation and reduce test time up to 4X.

This allows IC design teams to rapidly generate chips that are compliant with the IEEE 1838 test access standard for 2.5D and 3D IC architectures.

The Tessent Multi-die solution can also generate die-to-die interconnect patterns and enable package level test using the Boundary Scan Description Language (BSDL).

“IC design organizations are seeing dramatic spikes in IC test complexity due to the rapid adoption and deployment of designs featuring densely packed dies in 2.5D and 3D devices,” said Ankur Gupta, vice president and general manager of the Tessent business unit for Siemens Digital Industries Software. “With Siemens’ new Tessent Multi-die solution, our customers can be ready for the designs of tomorrow, while slashing test implementation effort and simultaneously optimizing manufacturing test cost today.”

“As the limits of traditional 2D IC design approaches become increasingly clear over time, more design teams are leveraging the power, performance and form factor advantages that 2.5D and 3D IC architectures can deliver,” said Laurie Balch, president and research director for Pedestal Research

“But deploying these advanced schemes in new design starts without first establishing a DFT strategy that acknowledges the inherent challenges these architectures present can raise costs and undermine aggressive timelines. However, by evolving DFT technology to keep pace with the rapid adoption of multi-dimensional designs, EDA vendors can play a key role in further enabling global, mainstream adoption of 2.5D and 3D architectures.”

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