Siemens boosts power verification in mixed signal tool

Siemens boosts power verification in mixed signal tool

Technology News |
By Nick Flaherty

Siemens EDA has boosted the power verification in the latest version of its Symphony mixed-signal simulation tool.

The Symphony Pro tool from Siemens Digital Industries Software now supports the latest Accellera standardized verification methodologies with a visual debug cockpit, resulting in productivity improvements of up to 10X compared to legacy solutions.  

The tool is designed to work with high level SPICE models that can speed up simulation of analog designs as part of a digital simulation of chips for automotive, imaging, IoT, 5G, computing and storage applications.

“One of the most important things is the lack of performance in golden SPICE models, so you need to strike a balance between accuracy and new methodologies to speed up the simulations,” said said Sathishkumar Balasubramanian, head of products for the analog mixed signal business unit at Siemens.

Instead the tool uses real number models, simplified models provided by the IP provider for elements such as DDR PHY, LVDS, SERDES, RF, PLLs and RFID blocks. “This models the analog circuit behaviour as a digital circuit which allows us to stay in a 100% digital flow,” he said. “You are doing top level modelling and taking advantage of the speed of the models so that when you assemble the IP you can take advantage of the verification suites.”

“The other domain that is really coming up is power aware verification,” he said. “The IEEE 1801 Unified Power Format is specifying power intent in power aware verification of an SoC. You need to think about power all the way form the architecture to the implementation with power domains, supply networks, power gating, corruption, isolation, retention logic, multiple voltages, level shifting, body bias and power states.”

The tool combines Siemens’ existing Symphony, which has over 80 tapeouts with 100 customers,  and Questa Visualizer platforms and adds industry-standard Universal Verification Methodology (UVM) and Unified Power Format (UPF) driven low-power techniques.

Customers include Silicon Labs.

“Our high-performance, energy-efficient chips designed for the IoT are analog intensive and mixed-signal in nature. To ensure high quality, we expanded our digital verification methodology to enable effective regression of our mixed-signal designs,” said Jayanth Shreedhara, senior CAD manager at Silicon Labs. “Symphony Pro Visualizer mixed-signal technology accelerated debug turn-around time for our digital on top UVM test suites, enhancing our verification productivity from days to hours and dramatically improving our coverage closure.”

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