Siemens claims breakthrough with 40bn gates of emulation
Siemens has re-architected its emulation and hardware assisted verification systems in a major change to emulate designs with up to 40bn gates.
The Veloce CS system has been developed by Siemens over the last five years to provide a consistent environment across emulation and prototyping with three linked system designs.
“We have been working on this for many years,” said Jean-Marie Brunet VP for Hardware Assisted Verification at Siemens EDA. “We have changed the design signifcantly with new hardware and software architectures.”
The development of custom AI chips and chiplets is a key driver for large emulation systems, he says.
“Although we hear Moore’s Law is dead it’s not the case, A lot of customers are going to very advanced nodes and 3D or 2.5D and chiplets and these complex ICs and systems all have fundamental issue with performance and power,” he said.“We have seen an explosion of purpose built SoCs and AI accelerators with different challenges. These have a tremendous need for emulation and prototyping. It is becoming the only platform that can verify the designs and this drove the change in architecture.”
So Siemens developed three hardware platforms that can be used in a continuum and a move away from custom system designs to blades that can be stacked in racks. “We are moving away from fixed chassis to a blade approach with fibre interconnect. We changed all the hardware for the emulation and prototyping,” said Brunet.
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The Veloce Strato CS uses Siemens custom 7nm Crystal X chip built at Samsung coupled with an architecture that scales up to 256 blades with 40bn gates with 4 x 4 connectivity. This gives a performance boost of 5x in throughput and in debug speeds.
“Crystal X is a brand new chip,” said Bruent. “Our previous was at 28nm and this is at 7nm and this is the maximum reticule that our foundry Samsung can do so it’s a very big chip. It also on the same process node as the VP1902 so we have closed that gap. We have a very good relationship with the foundry as we have tuned the core cell and the IP on the device.”
The Veloce Primo CS follows the same scaling and is aimed at enterprise verification and uses the VP1902 FPGA from AMD/Xilinx. This has 2 x2 cell routing that simplifies routing and debug for designs and scales to the same 40bn gates. The move to the VP1902 boosts the debug by 50x.
This also has lower power consumption and can be used in data centres with air cooled aisles.
“These use the same compiler with different place and route, so either we route to P&R to CrystalX or to the VP1902 for primo CS, everything else is identical,” said Brunet. “The only thing that is different is the logical mapping and we are reusing a lot of hardware between the two.”
The Veloce proFPGA CS uses a different blade approach smaller in size and aimed at the system software developers. This follows the acquisition of proFGA in 2021 and today there is proFGPA with the VP1902 for 2x performance and capacity. This provides emulation of designs up to 100MHz performance for a small single FPGA.
Veloce CS is qualified to run with the latest AMD EPYC CPU-powered HP DL385g11 servers.
“The evolution of SoC and system level design has brought about many changes in the last ten years that have made the use of hardware-assisted verification more necessary than ever,” said Alex Starr, Corporate Fellow at AMD which worked closely with Siemens on the architecture.
“We have been working closely with Siemens to incorporate AMD’s leading Versal Premium VP1902 device into the heart of the Veloce Primo CS and Veloce proFPGA CS systems for increased performance and scalability, as well as qualifying the AMD EPYC CPU-powered HP DL385 gen11 servers for use with the entire Veloce CS system. The Veloce CS system, including the Veloce Strato CS emulation platform, shows how Siemens responds to customer needs and showcases the innovation happening in the Veloce group.”
“Time to market is critical to the entire Arm partner ecosystem, emphasizing a need for tools that offer modularity, granularity and speed for IP and SoC verification,” said Tran Nguyen, senior director of design services at ARM.
“Siemens’ Veloce platforms have become an integral part of the Arm development process and we continue to see benefits of the new Veloce Strato CS system for hardware design acceleration and software development.”
“Veloce CS provides the industry’s only fully congruent, high-speed, modular hardware-assisted system with three systems,” said Jean-Marie Brunet, vice president and general manager, Hardware-Assisted Verification, Siemens Digital Industries Software. “With the Veloce CS system, we are addressing the specific needs of hardware, software, and system engineers who all play an essential part in delivering the world’s most advanced electronic products. By providing the right tool for the task, Veloce CS innovations speed up the entire verification process, and lower total cost of ownership, which can boost profitability.”
The Veloce Strato CS system is available now for selected partner customers. General availability of the three hardware platforms is planned for summer 2024. The Veloce CS system is planned to be cloud ready with general availability.
Veloce Hardware-assisted Verification System | Siemens Software
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