Siemens EDA, SPIL team on fanout chiplets
Siemens Digital Industries Software has teamed up with Outsourced Assembly and Test (OSAT) company Siliconware Precision Industries (SPIL) on chiplet package assembly.
The two are working on a planning and 3D layout vs schematic (LVS) assembly verification workflow for SPIL’s fan-out family of advanced IC packaging technologies. SPIL plans to deploy this differentiated capability across its 2.5D and fan-out package family technologies.
The packaging techniques such as 2.5D and 3D configurations combine one or more chips of different functionality with increased I/O and circuit density, which in turn requires the ability to create and review multiple assemblies and LVS, connectivity, geometry and component spacing scenarios.
To help overcome the challenges associated with deploying these advanced packaging technologies, SPIL is using the Siemens Xpedition Substrate Integrator software and Calibre 3DSTACK software for package planning and 3D package assembly verification LVS for its advanced fanout family of package technologies.
“Our challenge was to develop and deploy a proven advanced packaging assembly planning and verification workflow that included comprehensive 3D LVS,” said Dr. Yu Po Wang, vice president of CRD for Siliconware Precision Industries.
SPIL’s fan-out packaging family offers additional space for routing a higher number of I/O on top of the semiconductor’s area and extending the package size with a fan-out process, which cannot be achieved with conventional advanced packaging technologies.
“Siemens is pleased to collaborate with SPIL to define and deliver the workflow and technologies needed for their advanced packaging technologies,” said AJ Incorvaia, senior vice president of Electronic Board Systems at Siemens Digital Industries Software. “As SPIL’s customers continue to develop higher complexity designs, SPIL and Siemens stand ready to deliver the advanced workflows needed to bring these increasingly sophisticated designs to market.”
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