Siemens EDA taps Alphawave Semi for leading edge IP
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One of the notable differences between Siemens EDA and its competitors Synopsys and Cadence Design Systems is the lack of a leading edge IP offering. This has been pitched previously as not competing with their customers that develop their own IP and buy it from a range of sources.
No longer.
The division of Siemens Digital Industries Software has signed an exclusive OEM agreement to provide high-speed interconnect silicon IP from Alphawave Semi to customers.
Alphawave has IP platforms for connectivity and memory protocols such as Ethernet, PCIe, CXL, HBM, and UCIe (Die-to-Die) implementations, providing direct competition to offerings from Synopsys and Cadence. It provides 112G and 224G SERDES chip designs across multiple nodes and fabs for designs in 7nm, 6nm, 5nm and beyond.
“Our technologies play a critical role in reducing interconnect bottlenecks and this collaboration greatly expands our customer reach, allowing more companies to deliver next-level data processing,” said Tony Pialis, president and CEO, Alphawave Semi.
Siemens EDA also offers embedded memory compilers as well as foundational, or commodity, IP for CAN2.0, USB and Ethernet. It has previously focused on acquiring verification and validation IP for its tools from companies including Avery Design and Fractal Technologies.
Beyond the IP sales channel agreement, both companies will jointly engage with customers on the integration, which is a key challenge and a major overhead for IP developers. This is partly what led Alphawave IP to move away from the pure IP model and monetise that IP in silicon chiplets.
This agreement will accelerate customer access to Alphawave Semi’s silicon IP platforms via the Siemens EDA global sales force. Customers can license complete silicon IP building blocks including implementations of 3D-IC and chiplet-based technologies for AI, autonomous vehicles, data networking, hyperscalers and storage.
The deal covers IP for PHY, controller and subsystems. The PHY IP covers the Ethernet, PCIe, CXL and Die-to-Die applications from 1Gbit/s to 224Gbit/s in over 30 different industry protocols/standards. The MultiChannel/MultiRate Ethernet, PCIe, PCIe/CXL Combo, D2D streaming and HBM3E Memory Controller IP offers low power, area, and latency, while targeting applications in the datacenter, telecom, cloud computing, AI, NPU and 5G wireless spaces, combined into subsystem platform IP.
“The addition of Alphawave Semi’s silicon IP introduces industry leading technology to our customers, empowering them to achieve unprecedented advances across diverse industries in dramatically shortened timescales,” said Mike Ellow, CEO of Siemens EDA which is part of Siemens Digital Industries Software.
“Siemens Digital Industries Software is a key and trusted partner for AI and hyperscaler developers, and our agreement simplifies and speeds the process of developing SoCs for these, and other leading-edge technologies, to incorporate Alphawave Semi’s IP,” said Pialis.
www.awavesemi.com; eda.sw.siemens.com
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