Siemens models chip, package aging for digital twins
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Siemens EDA is developing models for the aging of complex chip packages over time as part of its tools to create digital twins up to the rack level. This is set to be launched in the next three months as part of the Calibre 3D range.
Alongside the Innovator3D IC tool, the Calibre 3DStress tool uses thermo-mechanical analysis to identify the electrical impact of stress at the transistor level. Together, these tools are intended to reduce the design, yield and reliability risks in complex, next generation 2.5D/3D IC and chiplet designs.
The impact of aging in chiplet design is particularly important with the mix of different process technologies, thinner die and higher power consumption combined with mounting on a substrate. With the thinner dies and higher package processing temperatures of 2.5D/3D IC architectures, chip and chiplet designers have discovered that designs validated and tested at the die level often no longer conform to specifications after packaging reflows.
The Calibre 3DStress starts at the chip level but is being extended to the package in the next six months to support digital twins at the rack level.
“Some of the failure modes are package driven,” said Shetha Nolke, senior product engineer at Siemens EDA. “We are starting with the die, but the aging is difficult to model quickly so there is still investigation on how to do that,” she said.
“Initially we see the tool used for sign off flows that start with packaging, and we see customers creating criteria for sign off in the next six months. Te digital twin gives multiple teams multiple views of the data so having a consistent digital twin provides consistency across the different design groups. If we extend that out we can expand it to include the board and the system as a continuum through to a rack.”
STMicroelectronics is using the tools in a global flow for qualitative development and quantitative sign off, she says.
“It’s a big change from a system on chip, not only from designing the die on smaller nodes but the SoC process is quite different from the packaging process,” she said. “There are thermal issues with operating at the higher power and there are process stages for the package that impose fixed constraints and higher temperatures than SoC, the die are thinner and the materials are more diverse so we bring the understanding of the full mechanical analysis.”
“We offer back annotation for circuit simulation so that the circuit extraction is stress aware, focusing on the chip to understand stress analysis and how it impacts on reliability. This helps optimise the IC placement to avoid reliability issues. We also offer a way to take the results and back annotate them to understand the impact of the stress on the die and package so that it will function as designed.”
The Innovator3D tool suite is comprised of the Innovator3D IC Integrator, a consolidated cockpit for constructing a digital twin using a unified data model for design planning, prototyping and predictive analysis; the Innovator3D IC Layout solution for correct-by-construction package interposer and substrate implementation; the Innovator3D IC Protocol Analyzer for chiplet-to-chiplet and die-to-die interface compliance analysis; and the Innovator3D IC Data Management solution, for the work-in-progress management of designs and design data IP.
The new multi-physics engine in Calibre 3DStress supports accurate, transistor-level analysis, verification, and debugging of thermo-mechanical stresses and warpage in the context of 3D IC packaging, allowing chip designers to evaluate how chip-package interaction will affect the functionality of their designs earlier in the development cycle. This not only prevents future failures but also optimizes the design for better performance and durability.
“In 2023, we adopted Siemens’ technology to meet the complex design and integration challenges of our advanced platform solutions. The Innovator3D IC solution suite plays a critical role in enabling the high-performance solutions we deliver to AI and HPC datacenters,” said Bryan Black, CEO of Chipletz, a leading fabless AI platform provider.
“Siemens EDA’s Calibre 3DStress tool can synthesize the complexity of components, materials and processes related to 3D IC architectures and can create accurate IP-level stress analysis. Using it, ST has been able to implement early design planning and sign-off flows, and accurately model potential electrical failures due to IP-level stress within a 3D IC package. The result is improved reliability and quality, together with a reduced time to market,” said Sandro Dalle Feste, APMS Central R&D Senior Director, STMicroelectronics
eda.sw.siemens.com/en-US/ic-packaging/3d-ic-design/
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