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SiFive aims for ARM with high performance RISC-V vector cores

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By Nick Flaherty


SiFIve has developed two families of RISC-V cores with vector processing for high volume applications such as wearables, smart home, industrial automation, AR/VR, and other consumer devices.

The Performance P670 and P470 RISC-V cores are designed to take on ARM’s Cortex A53 and A55 cores, Drew Barbier, senior director of product management at SiFive tells eeNews Europe.

“Customers are staying at A53, A55 – the  A510 is only used in mobile, and other ARMv9 cores are bloated and expensive,” he said. “We feel we have a significant frequency advantage over the ARM cores with 30% smaller area. This gives more options for implementation, a higher clock or more power efficient.”

“Wearables is a key market, this is the battleground. Customers have been wanting an upgrade to these products for a long time and it hasn’t come.”

The 64bit P670 core supports the RVA22 vector instruction profile with a 13 stage out of order instruction pipeline to give more power efficiency or more performance and can achieve 3.4GHz at  0.95V on a 5nm process technology.

The previous P650 was also out of order, and the 670 is built on that but tuned for area and power efficiency with an additional vector cryptography unit. There is also an optional private L2 cache to fit an application.

Both the 670 and 470 have support for virtualization, including a separate IOMMU for accelerating virtualized device IO and a new Interrupt Architecture (AIA) compliant interrupt controller, with better support for Message Signal Interrupts (MSI) and virtualization. They also support the WorldGuard system security.

The recent port of Android to RISC-V is a key step, he says. “Google has now started publicly accepting RISC-V patches in Android. This is the first barrier to entry so we think this is the turning point,” he said. “Now Google can target RISC-V and its up to the device manufacturers to be compliant with platform  – that’s the ISA extension and feature set of the core IP. The platform sits on top of that and specifies things at a system level and we work with partners to make it compliant

“Mobile is a longer term play but we are starting to see engagements. I would be surprised if we didn’t have that in the next three to five years,” he said.

“We expect customers in 7, 5 and 3nm,” said Barbier.

“The P670 and P470 are specifically designed for, and capable of handling the most demanding workloads for wearables and other advanced consumer applications. These new products offer powerful performance and compute density for customers looking to upgrade from legacy ISAs,” said Chris Jones, SiFive VP of Product.

www.SiFive.com/risc-v-core-ip

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