SiFive announces 4th generation of RISC-V Essential IP for embedded applications

SiFive announces 4th generation of RISC-V Essential IP for embedded applications

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By Jean-Pierre Joosting

SiFive is unveiling a major upgrade of its SiFive Essential product family at the RISC-V Summit Europe 2024. Developed over a decade, the field-proven Essential IP is already in use in billions of products including mobile phones, sensors, SSDs, FPGA platforms, surveillance cameras, smartwatches and more.

This full-portfolio refresh brings higher performance, improved power efficiency and more flexible interfaces, with configuration and integration options to cover virtually any possibility. The SiFive Essential Gen4 RISC-V products are available now.

“The best RISC-V embedded solutions just got much better with this fourth generation,” said John Ronco, SiFive SVP of Product. “With the benefits of cost-effective flexibility, performance and low power, RISC-V has won the battle for embedded. As legacy ISAs have reduced R&D and support, we are expanding SiFive’s broad portfolio of market leading Essential products and reaffirming our commitment and support for customers in these critical areas of innovation.”

SiFive has seen strong momentum across embedded segments where the Essential Gen4 products will bring impressive flexibility and features to enable customers to better tailor their designs. More than two billion SiFive RISC-V based chips for embedded devices have shipped to-date and the market continues to grow rapidly.

“The embedded space in 2024 represents a huge ($257 billion) market opportunity, growing with an 8.3% CAGR through 2030. RISC-V and SiFive have been increasingly gaining momentum and taking share from the other ISAs. SiFive is launching the products that these customers need while also innovating at the high performance and advanced AI levels,” said Rich Wawrzyniak, Principal Analyst at The SHD Group. “It is a mistake to discount the importance of embedded products as the flexibility and software portability of RISC-V makes designing products with multiple cores—including the highest performance cores—easier, creating a clear pathway for RISC-V into the next generations of high-performance chips.”

Key features of the Essential Gen4 IP portfolio include:

  • Broadest RISC-V CPU and system IP portfolio
  • Up to 40% runtime power reduction
  • 8 different baseline embedded 32-bit and 64-bit cores
  • From 2 stage single-issue to 8 stage superscalar
  • Improved L2 cache and enhanced L1 memory
  • Extensive configuration and integration options
  • CPU type, profile and options
  • On-chip memories selection
  • System, peripheral and front ports
  • Advanced power management and security
  • Debug and trace
  • Leading software support, including embedded Linux, FreeRTOS, Eclipse C/C++/ IDE

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