SiFive launches first RISC-V SoC

SiFive launches first RISC-V SoC

Technology News |
By Peter Clarke

The RTL code for the FE310 is downloadable for free from at The HiFive1, is an Arduino-compatible development board featuring the FE310 which is being offered through the Crowd Supply crowd-funding site at “donation levels” – in other words prices –  varying from $59 to $555. The higher donation levels get earlier delivery dates in December 2016 and the chance to have a telephone call with the founders of SiFive. Lower donations are expected to be rewarded with shipment in February 2017.

SiFive was founded in 2015 by creators of the RISC-V processor architecture, which is a freely available and open-source specification.  

The FE310 features SiFive’s E31 CPU, a 32-bit core running at 320MHz. Additional features include a 16kbyte L1 instruction Cache, a 16kbyte SRAM data scratchpad, hardware multiply/divide, debug module, one-time programmable non-volatile memory, flexible clock generation with on-chip oscillators and PLLs, and a variety of peripherals including UARTs, QSPI, PWMs and timers. Multiple power domains and a low-power standby mode ensure a variety of applications can benefit from the FE310, which was fabricated in TSMC’s 180nm manufacturing process.

The FE310 is the first member of the Freedom Everywhere family of customizable SoCs designed for microcontroller, embedded, IoT and wearable applications. The RTL code allows developers to customize their own SoC on top of the base FE310 core. For system architects, developers or companies without chip design capabilities, SiFive is offering a customization service, which it calls “chips-as-a-service.”

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