SiFive launches Linux-ready RISC-V quad-core processor
The Coreplex U54-MC contains four U54 CPUs and a single E51 CPU and is the first Coreplex processor core to offer multicore support and support for cache coherence.
The U54 cores support the RV64GC ISA with a five-stage, in-order pipeline ALU. The 64bit E51 CPU serves as a management core and is fully coherent with the U54 cores. The U54-MC Coreplex is ideal for applications which need full operating system support such as AI, machine learning, networking, gateways, and smart IoT devices.
The U54 cores come with 32Kbytes of instruction and data first level cache each while the E51 monitor core has a 4Kbyte instruction cache and an 8Kbyte DTIM. SiFive compares the U54 to the Coretex-A35 from ARM although SiFive stress that the U54-MC has real-time capabilities.
The U54 achieves a performance level of 1.7 DMIPS per MHz or 2.75 CoreMarks per MHz. In TSMC’s 28HPC manufacturing process single U54 core occupies 0.234 square millimeters while the Coreplex-U54 in a single-core configuration occupies 0.538 square millimeters. Typical achievable clock frequency at 0.9V is 1.5GHz while at worst case and voltage of 0.81V it can achieve 9
A development board based on U54-MC Coreplex IP will be available by 1Q18.
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