SiFive moves into RISC-V datacentre AI processor IP
SiFive has modified its high end RISC-V core for more scalability in datacentre AI chip designs.
The P870-D datacentre RISC-V IP is a variant of the previous P870 so that it scales to 256 cores and adds other features for datacentre AI chips.
The P870-D supports the open AMBA CHI protocol and other industry-standard protocols, including Compute Express Link (CXL) and CHI chip to chip (C2C) for heterogeneous system on chip (SoC) and chiplet configurations. SiFive is also working with Arteris for network on chip (NoC) implementations with a distributed and scalable IOMMU for accelerating virtualized device IO, which is also critical to address the latest functional safety and security requirements.
Reliability Availability Serviceability (RAS) features have also been added to the P870-D to to detect errors before an issue arises and protect data integrity, helping to prevent downtime and ensure the overall reliability of the system.
“This is our first real foray into a datacentre specific core,” Ian Ferguson, senior director at SiFive tells eeNews Europe. “What’s interesting is building something that is energy efficient with a CPU, vector engine and matrix maths and scales up to 256 cores rather than 16 on a single chip or on chiplets.”
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As well as the RAS the core includes larger 57 bit virtual memory support via the Sv57 extension and hardware virtualisation support for hypervisors using the RVA23 RSIC-V extensions.
“We want to focus on the compute sub-system and we have to be aware of trends in HBM and other things and that means some pretty strong third party relationships on roadmaps. Our take and the feedback we have from the market is that you can come up with a great chip architecture but the software that has been written is non trivial,” said Ferguson.
“Because we line up to RVA23 there’s a lot of software we can reuse but there are specific things around security with WorldGuard [developed by SiFive]. Xen, KVM and LInix will all work well but where it gets interesting is the scaling up with CPUs and we are doing a lot of work on the compilers, Middleware will align with the RISE RISC-V open source software consortium but we are working n the development tools to get it running well, and there is work with RISE on development tools on how those scale.”
“We have people taking our IP and implementing in 7nm in China and 3nm and we have done most of the modelling for 3nm,” said Ferguson.
The P870-D RiSC-V processor IP is sampling to lead customers now with a final production release by the end of 2024.
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