SiFive set to introduce next RISC processor architecture
The SiFive Intelligence architecture will feature a complete implementation of the latest RISC-V Vector (RVV) extension defined within the RISC-V instruction set architecture. It will be presented by Krste Asanovic, SiFive chief architect, at the Linley Fall Virtual Processor conference. The conference takes place Oct 20 to 22 and Oct 27 to 29.
SiFive Intelligence enables a single processing and development environment to be used for scalar and high-performance vector processing applications. The RVV is expected to extend the applicability of RISC-V to high-performance computing, artificial intelligence, and computer vision applications.
“SiFive Intelligence will offer a high-performance converged processor core capable of flexible execution of many workloads based on a single, industry-standard ISA,” said Chris Lattner, president of platform engineering at SiFive.
At the same conference Yunsup Lee, CTO of SiFive, is set to present and demonstrate a personal computer based on the upcoming FU740. It is not clear whether FU740 is a board or a development environment but SiFive claims it will allow developers to create RISC-V applications in a bare-metal environment, from OS to end-user application, using U7-series processor cores.
Related links and articles:
News articles:
SiFive design unit partners with ARM, others
ARM rival SiFive raises $61 million
SiFive creates global network of RISC-V startups
