Signal and power integrity, 3D-EM solving, and rule checking merged in single simulation environment
Aiming at high-speed digital PCBs, the company puts forward a tool that offers designers a complete set of analysis technology, spanning a wide range of underlying simulation engines and a graphical user interface (GUI) that supports both quick/interactive and exhaustive batch-mode analysis.
Rather than having to switch from one application to the next for different types of analysis, the new HyperLynx tool now offers 2D/3D signal and power integrity analysis in a single application, with one GUI. Users can simulate a critical SERDES channel one minute, and then by selecting a single new menu item, switch to analysis of a large power net’s decoupling.
Mentor has combined a very fast geometry extraction engine and advanced materials modeling (for wideband dielectrics, copper roughness, etc.) to produce highly accurate simulations. The new HyperLynx release implements a ‘decompositional’ analysis flow mixing 2D and 3D solvers to reduce simulation time by orders of magnitude compared to full-wave 3D. Multiple enginescomprising two 2.5D solvers,a fast DC/IR-drop simulator, and a fast quasi-static 3D solver merge to enable a full set of power-integrity features, all of which are available side-by-side in the same application as the HyperLynx signal-integrity capabilities. A second, more-advanced 2.5D solver is capable of pure power and mixed signal-and-power modeling, which can be used to add accuracy to SI simulations when simultaneous-switching-noise (SSN) complications are suspected.
The 3D engine is deeply integrated, so the user never has to learn the intricacies of a full-wave-solver environment. This integration ensures that signal and power structure geometries are passed; electromagnetic (EM) ports are formed; simulations are run; and S-parameter results are incorporated into time-domain simulations – automatically.
Tuning raw simulation capabilities to the specific requirements of standard interfaces and protocols (like DDRx memory and 100-Gb/s Ethernet SERDES) eases the user’s burden and provides streamlined, summary pass/fail judgment on entire interfaces. The HyperLynx wizard for DDRx memory interfaces pioneered easy setup, automated whole-bus simulation, and consolidated results reporting – and is now extended to DDR4 and LPDDR4 interfaces.
In the SERDES arena, protocols that support Channel Operating Margin (COM) allow checking the quality of links based on a specific, complex set of simulation steps for a single pass/fail number per-channel. The new HyperLynx tool is believed to be the industry’s first robust commercial implementation of COM for 100GbE signaling, with simulation details fully automated.
Visit Mentor Graphics at www.mentor.com/pcb/hyperlynx
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