SIGNAL CHAIN BASICS #51: Clock jitter demystified—Basic specifications in high-speed links (Part 2)
(Editor’s note: Click here for a complete, linked list of all previous installments of the series.)
This article addresses the impact of clock jitter on high-speed link performance. In Part 1, we provided foundational concepts of high-speed communications links. In Part 2, we discuss the basics of jitter budgeting.
Standards that convey increasingly large amounts of data over greater distances are constantly being developed. Committees and standards bodies comprising engineers from various interests establish jitter budgets based on the goals of the standard being developed (throughput and distance); while taking into account the limitations of the blocks that make up the communications link.
Figure 1 shows a typical high-speed communications link incorporating an embedded clock. Each subsystem (clock, transmitter, channel, and receiver) contributes to the overall jitter budget. Subsystem jitter includes a deterministic (DJ) and a random component (RJ) as shown in the Figure.
Figure 1 : Communications link – jitter components.
In order for acceptable (note 1) communication to occur, the following condition must be satisfied, Equation 1:
TJSYS(BER) ≤ 1 UI
Where:
TJSYS is the total jitter and
1UI is one unit interval (period of one bit)
Total jitter (TJ) includes the sum of deterministic and random jitter of each subsystem. Due to the nature of the random jitter, this summation requires special attention. Random jitter exhibits a Gaussian (random) distribution and is unbounded.
Therefore, random jitter is expressed as an RMS value and is evaluated within a specific bandwidth of measurement/integration. For example, the jitter measurement bandwidth of the receiver shown in Figure 1 is f2 – f1 (see Figure 2). This is because the receiver phase-locked loop (PLL) tracks jitter below f1 (thereby rejecting it), and the upper frequency limit of the transmit PLL is f2. From the receiver’s perspective, random noise that would degrade link performance falls between these limits.
Figure 2: High-speed communications link – random jitter measurement bandwidth.
Because random jitter is the result of stochastic processes, determining the total random jitter of the system requires a root summed squared (RSS) calculation as shown in Equation 2:
RJSYS = √ (RJCLK2 + RJTX2 + RJCH2+ RJRX2)
Determining the sum of the deterministic jitter sources is straightforward, Equation 3:
DJSYS = SJCLK + DJTX + DJCH + DJRX
Finally, estimating the total jitter of the system and, hence, the link budget is possible; however, some additional work is required. This calculation involves statistical mathematics. A parameter called Q-factor is employed (see Table 1).
Table 1: Q factor and bit error rate
Q-factor depends on bit error rate (BER) and is selected based on link performance/reliability goals. Due to the unbounded nature of random jitter, a bit error will (eventually) occur. For example, a BER of 10-8 means that one bit will be misinterpreted in error for every 100,000,000 bits transmitted. Modern communications systems typically require a BER that meets or exceeds 10-12.
The total jitter of the system (and hence the link budget) is calculated using Equation 4:
TJSYS = DJSYS + 2 × Q(b) × RJSYS ≤ 1UI
For example, for a BER of 10-14, the total jitter is Equation 5:
TJSYS(10-14) = DJSYS + 15.302 × RJSYS
This article discusses the parameters comprising the total jitter budget. The next time we talk about clocks, we will examine the relationship between random jitter and phase noise.
Join us for the next Signal Chain Basics article, when we will cover the drive capability of RS-485 transceivers.
References
- Data transmission with a known and acceptable number of bit errors (Bit Error Rate).
- It should be noted that the random jitter contribution of the channel is negligible if the system uses a passive implementation.
- For more information about clocking solutions, visit: www.ti.com/clocks-ca.
About the Author
John Johnson is the Manager of Market Development and Systems Engineering for the Clocks and Timing Group of Texas Instruments. John has 30 years of experience in the electronics industry and has worked in the fields of product development, marketing, systems engineering, and business management. He holds a MSEE from Purdue University. 
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