SIGNAL CHAIN BASICS #54: In audio clocks, who’s the boss, master, and slave?
(Editor’s note: Signal Chain Basics is an ongoing (and popular) series; you can click here for a complete, linked list of all previous installments of the series.)
When we covered audio topics here in the past, occasionally we mentioned I2S; I’ve done this in other articles I’ve written, as well many others in the audio field. In short, it’s a synchronous method of transferring stereo audio data from one point to another.
Most engineers believe that I2S has three different signals:
1. Data: as an input, or an output
2. Bitclock (BCK): the signal that establishes the boundary between adjacent bits in the data streams
3. Left/Right Clock (LRCK)/Wordclock: A slower clock, running at the sample rate, with a 50 percent duty cycle, which establishes the boundary between adjacent channels (left and right) in the data stream.
The unsung hero of I2S, and mostly ignored by digital signal processors (DSP) programmers and other processor junkies, is the master clock (MCK), which may also be called the system clock (SCK). The master clock (MCK/SCK), typically is a clock that is 64, 128, 256, 512 times the sample rate (FS). It can be provided directly through an input pin or it can be generated internally in some devices by a phase-locked loop (PLL).
Typically, DSPs don’t require an audio master clock, as they can be processing data at a completely different rate, and dropping data into output buffers (or receiving data through input buffers) at a rate driven by the BCK and LRCK.
Once you step outside of your processor, the audio master clock becomes much more critical. Most audio converters with MCK/SCK inputs require the clocks to be synchronized, while some are allowed to be out-of-phase. This means that they really need to be sourced from the same high-speed clock, and simply divided down. Some customers I’ve talked with have the brainwave, “Hey, my ADC needs an MCK, but it’s far away from my DAC. Therefore, I’ll use local crystal next to each converter.…” An understandable idea, but please: DON’T DO IT!
When you buy a crystal, you aren’t guaranteed that it’s exactly 48.000 kHz. Your analog-to-digital converter (ADC) crystal could be running at +5 percent accuracy and the digital-to-analog converter (DAC) could be running at –5 percent accuracy. This could spell disaster for your design! Read on to understand why.
Uses for master clock in audio ADCs
As shown in Figure 1, a high-speed master clock (e.g., 24.576 MHz clock) is used to drive the oversampling modulator in an ADC. The data from the oversampling modulator is then decimated down into the sample rate given by the LRCK.
When an ADC is running in master mode (generating the BCK and LRCK as outputs), then the ADC simply divides the MCK/SCK to generate the LRCK and BCK signals. Voila! The LRCK/BCK and master clock are synchronized – and probably in phase (unless it’s an unusual divider).
Figure 1: Generic ADC block diagram.
(Click on image to enlarge)
If the ADC is running as a slave, with an out-of-sync master clock, it will generate too much, or too little data for the digital decimator to fit properly into the output words. Many ADCs simply refuse to stream data under such conditions.
The case is the same for DACs. Figure 2 shows a high-level DAC diagram. Here, the interpolator needs to be run from MCK/SCK, which also drives the delta sigma modulator. If the MCK/SCK is not an integral multiple of the sample rate (64/128/256/512), then you’ll like get erroneous data on the output of the delta sigma modulator.
Figure 2: Generic DAC block diagram.
(Click on image to enlarge)
Where/how do I generate MCK/SCK?
In today’s industry, CMOS oscillators are favored by many, closely followed by crystal oscillators. They both provide very good accuracy, and low jitter. Voltage controlled oscillators (VCOs) are occasionally used, but can suffer from jitter in their output.
Many modern audio converters now integrate a PLL to generate MCK from a slower BCK. This is quite useful. However, you should be aware that with a PLL you will always introduce some chance of jitter, which can deteriorate audio performance.
Additionally, I’d suggest that given the option between having a crystal source drive the ADC, or a DAC, you should choose to run the ADC from a crystal-generated source. Once you’ve badly captured the input, there’s no amount of cleaning you can do get the good sound back! (You can’t polish mud!)
Therefore, my suggested rules are simply this:
1. If the converter is an I2S slave, you must provide the three I2S clocks (MCK, BCK and LRCK) all from the same source (or rely on an internal PLL, if there’s one in the converter).
2. If the converter is an I2S master, be sure to provide a reliable jitter-free MCK source. Then allow the converter to divide-down itself. Where possible, run the ADC from a trusted, low-jitter MCK source, in master mode. This will ensure the lowest jitter and minimize high-frequency distortion.
Suggested Reading:
- “On Jitter,” by Dan Lavry, Lavry Engineering, Inc., 1997.
- Learn more about audio solutions from TI at www.ti.com/audio-ca.
About the Author
Dafydd Roche is the home audio strategic marketing and systems engineer for the Audio Converter group at Texas Instruments. An avid musician in his spare time, Dafydd pours his passion and knowledge of audio and music-making into his work.
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
