SIGNAL CHAIN BASICS #58: Analyze the RL drive in an ECG front end using SPICE

SIGNAL CHAIN BASICS #58: Analyze the RL drive in an ECG front end using SPICE

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(Editor’s note: Signal Chain Basics is an ongoing (and popular) series; you can click here for a complete, linked list of installments #1 through #55 of the series, and here for all installments.)

(Also note: to see each image as an enlarged pdf, click on the word "enlarge" at the end of each caption.)

Electrocardiography (ECG) is the science of converting the ionic depolarization of the heart to a measurable electrical signal for analysis.  One of the most common challenges in the design of the analog electronics interface to the electrodes/patient is in the optimization of the right leg drive (RLD) for common mode performance and stability.  Leveraging SPICE to help in this effort can greatly simplify this process.

In an ECG front end, the RLD amplifier provides a common electrode bias at Vref and feeds back the inverted common mode noise signal (enoise_cm) to reduce the overall noise seen at the inputs of the instrumentation amplifier gain stage.  In Figure 1, the sources ECGp and ECGn are split to show how the RLD amplifier provides the common reference point for a portion of the ECG signal that is seen at the positive and negative inputs of the instrumentation amplifier (INA). 

Figure 1:  Simplified LEAD I with RLD connections (enlarge)

The parallel RC combination for the left arm, right arm, and right leg represents the lumped passive electrode connection impedance, which will be represented though the rest of this article as 52kΩ and 47nF.  Assuming enoise couples parasitically into the inputs, the feedback of enoise_cm will reduce the overall noise signal at each input, leaving the residual noise to be filtered externally or rejected by the common mode rejection ratio (CMRR) of the INA. 

The variation in common mode rejection can be seen in Figures 2, 3, and 4, which show the common mode test circuit with varying gain of the RLD amplifier.  These plots show that the best low-frequency CMRR is achieved with no feedback resistor (i.e. infinite gain); however, in reality, eliminating the DC path and/or setting RF to a high value may not be practical for applications that require linear operation of the RLD amplifier when one of the input amplifier leads is removed. 


Figure 2:  CMRR vs. RLD gain (enlarge)


Figure 3:  Plot of CMRR vs. frequency and RLD gain (RF) (enlarge)


Figure 4:  CMRR RLD vs. no RLD (enlarge)

Once the gain of the RLD amplifier has been determined, the next step is to use the test circuit in Figure 5 and inject a small signal step in the loop and monitor the output response.  In this case, the response (displayed in Figure 6) shows a strong output oscillation indicating instability in the loop. The dominant feedback path causing this instability is the body/electrode/INA feedback path around the RLD amplifier. 

Figure 5:  Small-signal pulse test circuit (enlarge)


Figure 6:  Output plots for Figure 5 (enlarge)


Figure 7 shows a test circuit that allows the feedback and the open loop gain (AOL) curve of the RLD amplifier to be separated and analyzed on a Bode plot. 


Figure 7:  Test circuit of electrode/INA feedback (enlarge)

Note that without an external compensation network the 1/β curve approaches the AOL curve at with a rate of closure (ROC) >20dB/dec, indicating instability (the proof of this criterion is not discussed here). 

The fix for this issue, shown in Figure 8, is to add a series Rc and Cc in the local feedback of the RLD amplifier (Zc in Figure 9).  Zc then becomes the dominant feedback path between 20k-30kHz. The result for the simulation in Figure 7 is represented by the 1/β (feedback) curve of Figure 9. 

Figure 8:  Test circuit for compensation network (enlarge)

Figure 9:  AOL, 1/β, and Zc (enlarge)


Figure 10 shows the full circuit of the right leg drive with compensation. The new, compensated 1/β plots (based on variations in Rc and Cc) are shown in Figure 11.  The overall 1/β intersects the AOL curve with a ROC that is ≤ 20dB/dec and a loop gain with >45° phase margin (Figure 12).


Figure 10:  Compensated right leg drive (enlarge)


Figure 11:  AOL and 1/β for different values of Cc (enlarge)


Figure 12:  Loop gain and phase for Figure 10 (enlarge)

In summary, SPICE can be a useful tool to quickly help analyze and optimize the performance and stability of the RLD front-end circuitry.  Keep in mind that the simulation can only be as good as the models, so it is important to model key specifications, such as noise; AOL; open loop Zout; and CMRR vs. frequency, correctly and up front before analysis and design.


•Brown, John and Joseph Carr,  Introduction to Biomedical Equipment Technology, Prentice Hall Inc.,  New Jersey  1981, 1993.

•Dubin, Dale, Rapid Interpretation of EKG’s, Cover Publishing Company, Fort Myers 2000.

Green, Timothy, Operational Amplifier Stability, Part 2 of 15:  Op Amp Networks, SPICE Analysis,

About the author
Matthew William Hann, Precision Analog Applications Manager at TI, has more than a decade of product expertise which includes temperature sensors, difference amplifiers, instrumentation amplifiers, programmable gain amplifiers, power amplifiers, and TI’s line of ECG AFE devices. Through his role as an applications engineer, Matt has developed a focused expertise on the design of analog front ends for medical applications such as ECG, EEG, EMG, blood glucose monitoring, and pulse oximetry. Matt received his BSEE from the University of Arizona, Tucson. He can be reached at




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