Signal-quality analysis for next-generation transmission technologies
Transmission technologies for implementing high-speed, large-volume transfers are centred on PAM (pulse amplitude modulation) methods, which offer both faster symbol rates than earlier NRZ signal methods and increased transmission capacity without increased symbol rates.
This article describes a new measurement platform supporting next-generation network transmission standards such as 100GbE, 200GbE and 400GbE as well as the latest and future high-speed serial interface standards, such as PCIe Gen4 and Gen5, Thunderbolt Gen3 and USB Gen3.1.
Telecom and datacom trends
The trends that are driving the telecom and datacom sectors, and hence the requirements for test and measurement equipment, can be summarised under the following categories:
- Higher speed, smaller size and lower power consumption are key drivers for the optical interfaces of leaf and spine switches on high-end servers and storage devices.
- Enhancements for high-speed inter-equipment interfaces, including advanced semiconductor devices, network interface cards, and optical modules for 25GbE, 50GbE, 100GbE, 200GbE and 400GbE communications.
- The PCIe Gen4 (16GT/s) standard for bus/backplane interfaces in network interface cards, which has just been ratified.
- PAM4 (pulse amplitude modulation) transmission, now becoming widely adopted to increase bandwidth in 50G/200G/400GbE systems and likely to migrate into next-generation solutions for other standard interfaces such as Infiniband, Thunderbolt and PCIe Gen5 in the near future.
As a result, both network equipment manufacturers and the semiconductor industries are becoming focused on the integration of high-speed Ethernet and high-speed serial bus connectivity on the same boards and chipsets, thus requiring validation capabilities for all the related technologies.
From a test & measurement viewpoint, the most important focus today is the need for signal-integrity evaluation for research & development on PAM4 systems in the semiconductor and optical module industries, along with capability to test multiple signal channels simultaneously, and with additional test functions in areas such as PAM emphasis, signal equalisation, and jitter tolerance verification (Figure 1).
Telecom: baud-rate 56G, PAM4 modulation, multi-channel and BER with equalisation and FEC;
Server/storage: Merged 100GbE and BUS Link Training Technology for electrical short reach;
HS-BUS: High bit rate (PCIe-G4) for server backplane, and supporting USB Type-C and TBT-3 Ifs.
All-in-one solution
Traditionally, the challenges presented by these vastly differing requirements would have been addressed by using discrete instruments to handle the different test environments of each application sector. Now, however, all-in-one solutions are emerging that will carry out accurate measurements on next-generation high-speed electronic and optical devices – including the optical transceivers and modules used in high-end servers and communications equipment for M2M and IoT applications.
Typical of these solutions is the system shown in Figure 2, which is based on a high-performance bit error rate tester (BERT) that can accurately evaluate high-speed interface designs during the early development stage. This instrument can measure the performance of network-side interfaces at speeds of 400 GbE, 200 GbE, and 100 GbE, as well as internal PCI Express bus interfaces, to help speed design evaluation times and lower the overall cost of test.
It now becomes possible to address all the emerging test requirements for the telecoms, data centre and storage network sectors, plus high-speed serial Bus segments, on the same multichannel platform. This uses a modular approach combining a mainframe unit with plug-in modules that support multiple applications via a range of both hardware and software options, leading to a solution that offers flexibility over time and support for long-term users’ return on investment.
Accuracy and reliability
As an illustration of the accuracy and reliability of the measurement results provided by this latest generation of test instruments, the pulse pattern generator has an intrinsic jitter of typically 115 fs RMS, as well as a typical Tr/Tf of 12 ps. Other key specifications include a peak-to-peak jitter of typically 6 ps maximum, and typical input sensitivity of the internal error detector of 15 mV.
Complementing this high performance are support for integrated multi-channel testing up to 16 channels 32Gbps, and multiple features that improve accuracy and efficiency. For example, a link negotiation function supporting high-speed digital interface standards connects the test instrument to the device under test for improved bus interface evaluation. Engineers can use this function to conduct PCI Express Gen 1 to Gen 4, and future Gen 5, tests, LTSSM status analysis, jitter generation, and CM/DM noise injection. A jitter measurement function evaluates signal integrity, while a 10Tap emphasis function and equaliser function can be used to characterise test signals according to transmission path loss.
The test system can also be configured with peripheral equipment for expanded measurement capability. For example, an integrated solution combining the BERT tester with other instruments can support generation of the 32 Gbaud and 64 Gbaud PAM4 signals required for 200 GbE and 400 GbE measurements, BER measurements, jitter and amplitude noise injection, and emphasis addition, for versatile future-proof standards support.
Collaborative solutions for future-proofing
The ease of adding hardware and software options to the latest generation of test instruments means that future developments in the various communication standards can be accommodated as they are updated. Similarly, it becomes a fairly straightforward process to integrate the BERT signal-quality analyser with other types of test equipment to provide integrated solutions for specific test requirements. One example of this approach is provided by a partnership between Anritsu and Teledyne LeCroy to provide a comprehensive PCI Express® 4.0 (PCIe Gen4) test solution by integrating the Anritsu MP1900A signal quality analyser with the Teledyne LeCroy LabMaster 10Zi-A oscilloscope and QPHY-PCIe4-Tx-Rx software (Figure 3).
This comprehensive system provides high-speed IC, device, and network engineers with one complete solution to conduct automated transmitter and receiver compliance tests, as well as link equalisation verification.
The Anritsu/Teledyne LeCroy solution can be easily expanded to 32 Gbit/s, making it the first end-to-end solution to address PCI Express 5.0 (PCIe Gen5) requirements. The system will also support PCI Express 3.0 (PCIe Gen3) transmitter, receiver and link equalisation testing for complete PCI Express ecosystem coverage.
The Teledyne LeCroy oscilloscope provides the necessary 25 GHz bandwidth for PCIe Gen4 transmitter testing and receiver test calibration, and may be upgraded in bandwidth to support next-generation serial standards at 32 Gbit/s and higher. The LabMaster 10-25Zi-A and the forthcoming QPHY-PCIe4-Tx-Rx software option perform all necessary automation and control for PCIe Gen4 transmitter, receiver, and link equalisation testing in conjunction with the Anritsu analyser, including fully automated software controlled calibration. Debugging of PCI Express interfaces is simple and intuitive with integrated eye diagram and jitter analysis tools and PCI Express decoding with waveform annotation and tabular analysis.
This combined solution fills the market void for a complete physical layer PCIe Gen4 test system that can be easily expanded to PCIe Gen5 as the market continues to develop technologies for high-speed networks.
PCIe Gen4 represents a significant test challenge for design engineers, and this collaborative system leverages two best-in-class instruments to accurately measure and validate product performance in accordance with the PCI-SIG standards. Moreover, recognising that PCIe Gen5 is expected to emerge within two years, it protects users’ investments by creating a clear and efficient upgrade path that will help to control future test costs.
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