Silicon IP builds NVM at 180 nm: enables mixed-signal trimming, calibration
DesignWare AEON Few Time Programmable (FTP) Trim Non Volatile Memory (NVM) IP for TowerJazz 180 nm SL process technology integrates high voltage generation and control circuitry using a standard CMOS technology without the need for additional masks or processing steps.
The IP operates from a single core supply, eliminating the complication of providing a separate voltage for NVM programming. The DesignWare AEON FTP Trim NVM IP provides the smallest area for precision analogue IC trimming and sensor calibration applications, in a similar footprint as one time programmable (OTP) solutions with the advantage of reprogrammability.
“Synopsys DesignWare AEON FTP Trim NVM IP enabled us to meet our customers’ aggressive schedule requirements and need for small reprogrammable non volatile memory IP in the TowerJazz 180 nanometer process technology,” said Tal Bar (Dotan), director of IP Design Services at TowerJazz.
The reprogrammability advantage of the NVM IP enables designers to make in-field calibration updates, which allow end customers to make customisations and changes. The NVM IP includes necessary support and control circuitry including all high voltage generation and distribution required for programming to reduce system design complexity and IC area. It also supports up to 1 k bit instances, up to 10,000 write cycles, and more than 10 years of data retention at a temperature range (-40°C to +125°C) for industrial applications.
DesignWare NVM IP is also available for multiple other foundries in 250 nm to 40 nm process technologies.
Synopsys; www.synopsys.com/designware
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