Silicon-on-insulator technology research funded in ENIAC European project
Led by STMicroelectronics, Places2Be (Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe) aims to support the deployment of a FD-SOI pilot line at 28 nm and the subsequent node, as well as a dual source that will enable volume manufacturing in Europe. Places2Be will drive the creation of a European microelectronics design ecosystem using this FD-SOI platform and explore the path towards the next step for this technology (14/10 nm).
FD-SOI is a low-power, high-performance next-generation alternative to conventional silicon and FinFET technologies. The first FD-SOI systems-on-chips are expected to be used in consumer electronics, high-performance computing and networking.
With a budget of about €360m, the participation of 19 partners from seven countries, and the planned involvement of about 500 engineers over three years across Europe, Places2Be is the largest ENIAC Joint Undertaking project to date and is supported as well by the National Public Authorities in the participating countries. Places2Be is one of the key enabling technologies (KETs) pilot-line projects contracted by the ENIAC JU to develop technologies and application areas with substantial societal impact.
The FD-SOI manufacturing sources for the project are located in each of the two largest European microelectronics clusters: the pilot line in STMicroelectronics’ Crolles fab (near Grenoble, France) and the dual source in GlobalFoundries’ fab 1 in Dresden (Germany).
“The Places2Be project will reinforce the ecosystems of both Grenoble and Dresden clusters, while also positively impacting the whole value chain of microelectronics in Europe – large companies, SMEs, start-ups and research organisations – beyond the direct impact induced by the material and IP investments,” declared François Finck, Director of ST’s R&D cooperative programs and project coordinator.
STMicroelectronics: www.st.com
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