Single-chip dual transceiver software-defined tunable over 70 MHz to 6 GHz

Single-chip dual transceiver software-defined tunable over 70 MHz to 6 GHz

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By eeNews Europe

The AD9361 is a monolithic software-defined radio chip that contains two complete transmit and receive channels, can operate anywhere in the spectrum from 70 MHz to 6 GHz, and with channel bandwidths from 200 kHz to 56 MHz. In designing it to enable programmable radio applications that operate over a wide range of modulation schemes and network specifications such as defence electronics, instrumentation equipment and communications infrastructure.

An ADI spokesman disclosed that the device has in fact existed for some time, and is already the basis of products developed by a limited customer group, and that Analog has now chosen to make it available to a wider market. In part, the spokesman explains, this approach has been driven by the fact that applications for the SDR chip are so diverse that the company has had to grow an infrastructure and design-support package so as not to have its own design-support facilities overwhelmed by customer requests.

Accordingly, the AD9361 is supported by a wide range of design resources to expedite time to market including a software design kit and FPGA mezzanine card (FMC) to rapidly develop software defined radio solutions. One of the early customers quoted by ADI is Ettus Research, a National Instruments company; President Matt Ettus comments, “The AD9361 Agile Transceiver is a complete RF transceiver solution on a single chip – it’s an RF architect’s dream device…we combined it with a Xilinx Spartan-6 FPGA, USB 3.0 interface and comprehensive software support, to create easy-to-use and flexible software-defined radio solutions.”

The transceivers integrate an RF front end with a selection of low-noise-amplifiers, flexible mixed-signal baseband section, frequency synthesisers, two analogue-to-digital converters and two direct conversion receivers. Functional blocks are combined, alternate blocks such as LNAs selected and parameters (such as local-oscillator frequencies – there are full fractional-N synthesis LO blocks on-chip) set according to the needs of any given signal, and everything can be changed and reconfigured on-the-fly. Among other capabilities, you can build a complete 2×2 MIMO configuration with the chip.

Two independent direct conversion receivers have a state-of-the-art noise figure and linearity. Each receive subsystem includes independent automatic gain control, DC offset correction, quadrature correction, and digital filtering, eliminating the need for these functions in the digital baseband. The AD9361 also has flexible manual gain modes that can be externally controlled.

Two high-dynamic-range A/D converters per channel digitise the received I and Q signals and pass them through configurable decimation filters and 128-tap FIR filters to produce a 12-bit output signal at the appropriate sample rate. The transmitters use a direct conversion architecture that achieves high modulation accuracy with ultra-low noise.

Design resources include a Software Design Kit and FMC Board. Together with the FPGA mezzanine cards, ADI offers a range of AD9361 design resources including Gerber files, code references, Linux sample applications and drivers, and design support packages, which are available for download.

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