Single memristor provides 11-bit memory device

Single memristor provides 11-bit memory device

Technology News |
By Peter Clarke

A US research team has reported a ‘de-noising’ process that improves the performance of an analog memristor device so that 2,048 levels of conductance can be read.

The ability to store up to 11-bits in a single-device could lead to radical increase in memory capacity and a corresponding reduction in power consumption needed for AI hardware.

The team’s paper in Nature describes the impact of electron-trap defects in a phase-change type of memory. It also reveals detail of the TetraMem computing memristor, a critical component of TetraMem’s analog in-memory computing accelerator for AI/ML.

The team was led by Joshua Yang, Professor of Electrical and Computer Engineering at the University of Southern California, and a co-founder and scientific advisor at TetraMem.

Professor Yang, with researchers from USC, Massachusetts Institute of Technology, and the University of Massachusetts, developed a protocol for devices to reduce “noise” and demonstrated the practicality of using this protocol in a 256 by 256 device array. This demonstration was made at TetraMem, a startup company co-founded by Yang and his co-authors (Miao Hu (CTO), Professor Qiangfei Xia, and Glenn Ge (CEO), to commercialize AI acceleration technology.

The team claims that their device is the best non-volatile memory/memristor yet produced for edge AI applications.

Metal-oxide cross-point switch

The device is a metal-oxide based cross-point switch. The device is made of a mixture of Al3O2, above a layer of HfO2 sandwiched between a tantalum/titanium top electrode and a platinum bottom electrode. Each of the bilayers is less than 1nm thick so that after being laid down they appear to form a mixed layer rather than two separate continuous layers. The device was fabricated in a 240-nm diameter via above the CMOS peripheral circuitry.

Conductive channels are formed in the material by applying a set voltage and that can be at varying levels of strength. The authors propose that the conductive and insulating phases of the metal-oxide material relate to the orthorhombic phase with a high number of oxygen vacancies and the monoclinic phase without oxygen vacancies, respectively.

While it has been possible to report multiple read levels in such devices previously the fluctuations of conductance and level of noise has kept this to fewer than 200, the authors report. This is likely due to the creation of multiple incomplete channels.

A key development reported in this paper is that by applying a series of electrical pulses it is possible to suppress the fluctuations and increase the number of observable conductance levels by an order of magnitude. In addition, this ‘denoising’ process does not require any extra circuitry beyond the conventional read and write circuits. The application of the appropriate voltage in the denoising process either annihilates or completes these incomplete channels, resulting in a reduction in fluctuation.

A further positive indicator is that the team made ICs with 256 by 256 memristor arrays monolithically integrated on CMOS on 200mm wafers in an undisclosed commercial foundry. An individual memristor on the chip was tuned into 2,048 resistance levels by high-resolution off-chip driving circuitry, and each resistance level was read by a dc voltage sweeping from 0 to 0.2V.

Scaling with geometry?

One matter not discussed in the paper is how the number of conductance levels achievable scales with the size of the via.

Via email correspondence with eeNews Europe Professor Yang said: “Although the device total area is 240nm in diameter in this paper, the active region that responsible for the switching and conductance levels was actually about tens of nanometer (in diameter), which means the conductance levels would be the same even if the device size was tens of nanometer.”

Professor Yang added: “We haven’t systematically studied how the conductance levels scale with device size experimentally. In principle, when the device is scaled down to sub-10nm, we would still have thousands of atoms in the active region of the device and the atoms have thousands of positions to go, which should still lead to sufficient numbers of states (i.e., conductance levels).

Related links and articles:

The article at can be read here:

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HP helps birth analog-in-memory processor startup

Chinese startup raises funds for in-memory AI

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China startup Witinmem uses analog flash for compute-in-memory

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