SiPearl delays Rhea1 supercomputer chip to 2025

SiPearl delays Rhea1 supercomputer chip to 2025

Business news |
By Nick Flaherty

European supercomputer chip designer SiPearl has delayed its Rhea1 chip further.

SiPearl is now planning to have first samples of its Rhea1 supercomputer chip in 2025.

The company has confirmed that the Rhea1 chip will have 80 ARM Neoverse V1 cores each with two Scalable Vector Extension (SVE) units of 256 bits per core with the ARM Neoverse CMN-700 Coherent Mesh Network on Chip (NoC) as well as built-in High Bandwidth Memory with 4 stacks of HBM and four DDR5 interfaces to handle memory-bound AI frameworks such as transformers.

The first version of Rhea was originally planned for the end of 2022 and back in October 2023 Rhea1 was expecting to tape out in early 2024 with sampling later this year for the Jupiter supercomputer centre in Germany.

Rhea1 is supported by a wide range of compilers, library and tools, from traditional programming languages such as C/C++, GO and RUST to modern AI frameworks such as TensorFlow or PyTorch.

“Combining the performance and energy-efficiency of arm® Neoverse V1 cores with in-package HBM and embedding SiPearl patented memory and power management schemes, Rhea1 will fulfill the mission entrusted by EuroHPC JU and the European Processor Initiative consortium: to bring dedicated high-performance microprocessor technologies back to Europe. Rhea1 will be a world class microprocessor for HPC and AI inference. In the fast-growing generative AI market, it will be a great alternative to existing solutions for AI inference workloads at lower cost while offering higher flexibility to model changes,” said Philippe Notton, CEO and founder of SiPearl.

However the latest AI chips are being developed with the V3 Neoverse cores and HBM 2e memories.

The company has more than 190 people in France (Maisons-Laffitte, Grenoble, Massy, Sophia Antipolis), Germany (Duisburg) and Spain (Barcelona). It is opening its third operational subsidiary outside of France in Bologna, Italy. Bologne is host to Cineca, the largest Italian supercomputing centre, a partner in the European Processor Initivative (EPI) consortium.

The next phase of the EPI project with SiPearl is aiming to produce the specification that defines the hardware Common Platform for the chip and system integrating technologies to address the need for designing decoupled systems combining hybrid compute units, or chiplets.

This will look at interfaces such as the latest CXL, CCIX, and PCIe and analyse the die-to-die interfaces for chiplet-chiplet interconnects such as bunch of wires (BOW), UCIe and XSR.


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