Specialist foundry SkyWater Technology Inc. (Bloomington, Minn.) has announced the availability of two SRAM compilers for its 90nm rad-hard manufacturing process.
SkyWater’s RH90 process is based on MIT Lincoln Laboratory’s 90 nm FDSOI CMOS process technology with enhancements including dual gate transistors and copper dual damascene interconnect.
Mobile Semiconductor Corp. (Seattle, Wash.) is providing both single-port and dual-port SRAM compilers for the soft error resistant fully depleted silicon on insulator (FDSOI) technology. The combination is suited to customers developing space, defense and high-reliability products.
Strategic rad-hard performance is achieved using dual interlocked storage cell elements (DICE). These compilers incorporate additional innovative rad-hard by design (RHBD) techniques including triple mode redundancy (TMR), DICE latches, and critical charge analysis to reduce single event transients (SET) and single event upset (SEU). The compiler also implements bit separation to reduce multi-bit upset (MBU). Optional multi-bit error detection and single-bit error correction is available to reduce soft error rates even further.
The offering is partly a result of a $170 million investment by the Department of Defense (DOD) to increase US capability to manufacture strategic rad-hard electronics domestically.
Multiproject wafer (MPW) runs are available.
Mobile Semiconductor’s CEO, Cameron Fisher said, “Mobile Semiconductor has been providing radiation hardened memory compilers to the aerospace industry for over 14 years. We are excited to be working with SkyWater as they set a new standard for hardened microelectronics. I am confident that the performance of these two new rad-hard memory compilers will be of great value to SkyWater’s RH90 customers.”
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