SLX FPGA 2020 features C++ analysis and array partitioning

SLX FPGA 2020 features C++ analysis and array partitioning

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By eeNews Europe

These enhancements extend SLX FPGA’s ability to analyze C/C++ code further, make better decisions, and further accelerate performance.

An example of the performance improvements is demonstrated in Silexica’s latest white paper, SLX FPGA Beamformer. It shows how SLX FPGA optimizes an algorithm used for beamforming in radar applications and achieves more speed-up compared to an expert-level hand-optimized HLS implementation in less time.

“SLX FPGA takes the guesswork out of high-level synthesis design,” said Philippe Manet, CEO of ECSPEC. “Since adding SLX FPGA to our design methodology, we’ve significantly reduced our development time. In one of our designs, a complex image processing algorithm, we were able to achieve better performance with SLX in one week compared to hand-coded RTL, which took two months.”

Adopting an HLS methodology presents challenges that must be considered and overcome during the design process. SLX FPGA tackles the problems associated with the HLS design flow, including non-synthesizable C/C++ code, non-hardware aware C/C++ code, detecting application parallelism, and determining which pragmas to insert and the pragma attributes to help engineers prepare and optimize their C/C++ application code for HLS.

Silexica –

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