Smaller chip architectures make digital power an imperative
Moore’s Law is set to come to an end. The end of Moore’s Law, where transistor density doubles approximately every two years, has been reportedly just a few years away for what seems like decades now.
TSMC’s smallest architecture is a 20nm process, which it claims has "30 percent higher speed, 1.9 times the density, or 25 percent less power [compared with] its 28nm technology." Intel is claiming similar process geometries.
Shrinking nodes to this level creates several difficulties.
Digital power – from system level down to the chip
The importance and number of implementations of digital power have been growing steadily over the past decade and, when fully implemented, it allows users to dynamically adjust power rails to improve efficiency, quickly make changes during development to shorten design cycles, and receive real-time telemetry to let users accurately analyze their power infrastructure.
Typically, this has entailed a complete system level solution involving both hardware and software implementation. The companies that have made the transition to digital power have seen incredible benefits and realized a distinct advantage, but the majority of these companies have also had the infrastructure and resources to manage an implementation at the system level.
This type of implementation is not necessarily a trivial task without having proper information and partners to work with. Thus, the move to a fully-digital power system has been slower than the market had hoped.
While the majority of the vendors in the digital power market have tried to drive the value of a complete system solution, the fact is that it can also provide incredible value at just a single socket level. There are now numerous chips with extreme power requirements of 50A, 70A, or even over 100A @ less than 1V, capable of handling significant transients and very tight tolerances on output.
Typically these challenging power requirements have resided at the processor market, but they are now migrating to other mainstream and application-specific ICs. These are perfect scenarios for a highly integrated digital POL.
Digital POLs like the PMBus-compatible NDM2Z series DC-DC converter module incorporate power management features like voltage sequencing, voltage margining, and voltage tracking to help designers dynamically optimize their power systems.
Recommended, highly recommended or required
Recommended, highly recommended, and required are terms that are consistently thrown about in datasheets and marketing materials at all levels. Unfortunately, there isn’t an IEEE definition for these terms, and it is up to the user to interpret the vendor’s meaning.
For the most part, no one likes to use the word required in their technical documentation because that locks it in as part of the solution and could potentially be used against them by their competitors. For example, in the two scenarios above, it could be considered that digital power is recommended for a system and highly recommended for those chips with the extreme power requirements. Simple and straightforward, right?
Required is not a term that has been synonymous with digital power outside of an Intel serial VID (SVID). However, there has been an "under the radar" movement in the semiconductor industry to begin requiring a "dynamically adjustable" output voltage. I have personally watched this movement evolve, beginning with ASICs and now migrating to general release ICs. This has come as a surprise to most engineers, leaving them scrambling to find a solution for this new requirement.
As further evidence of this movement, the PMBus working group recently announced and presented a proposed transition to a v1.3 of the PMBus specification as well as a new PMBus+ that would add an Adaptive Voltage Scaling Bus (AVSBus) to the new revision. The AVSBus is an additional 3-wire serial bus that is considerably faster, up to 50 MHz than the existing SMBus, used specifically for voltage scaling. While the v1.3 PMBus specification allows for a faster SMBus, up to 1 MHz, it is still not fast enough for the "immediate" need to change a voltage.
These updates to the PMBus specification will allow the industry to standardize to the new requirement rather than continuing to implement a series of proprietary solutions now required by some of these chip vendors. (For more information on PMBus and the proposed changes and addition of AVSBus, go to www.pmbus.org.)
Chip variability
So, what is driving this dynamically adjustable power supply requirement? From our experience, we are seeing three dominate factors – improved performance, power savings, and wafer yield increase. In reality, the first two are still considered optional, but highly recommended… the latter is the driving force behind required.
One of the most critical factors driving the cost of semiconductors is the billions of dollars needed to build a state-of-the-art fab and the associated operational costs to keep it running. Couple that with the sensitivity and complexity of 32nm (and less) circuits, and you end up with the need for a finely-tuned and tightly restricted core voltage requirement.
These tight restrictions significantly impact the yields that they are capable of from each wafer. One of the ways they have discovered to increase yields is to require a dynamically adjustable core voltage. Here is an example:
- A DSP has a core voltage requirement of 1.0V and a limit of ±2% accuracy on the core voltage supply over all conditions. At the end of the manufacturing process, the manufacturer tests each chip at 1.0V plus or minus a very small margin to verify performance to specification. Anything that operates outside of that specification is discarded because it is considered to not meet spec.
- Unused chips are expensive to discard. However, just because they couldn’t meet the 1.0V requirement doesn’t mean that they can’t meet the performance specification… it just can’t achieve it at 1.0V. But, if you were to allow for a voltage of 0.97V or perhaps 1.02V, that once discarded chip is now within performance specification and useable.
Chip companies are therefore running an "integration algorithm" to define optimal core voltage either at the time of chip test or at the time of board power-up. Once that is established, the optimal core voltage requirement is sent to the point of load controller via a digital communication bus sometimes utilizing proprietary commands.
In some instances, an additional MCU is used to translate the proprietary command to a standard PMBus command. After the controller receives the command to set the output voltage to "X", it will then run at the new optimized voltage for the rest of time. By doing this vendors are increasing yields on their chips and driving cost down.
The effect of the PMBus+ specification
The AVSBus and adaptive voltage scaling has multiple application usage for power savings, but the usage that seems to be the most relevant and immediate is for the scenario previously described. This is the scenario that creates a “required” environment. The new PMBus+ specification with the AVSBus is expected to go into effect in March 2014. Once this occurs, we can expect to see the next wave of chips requiring digital power to not only improve yields, but also to maximize performance and reduce power consumption.
Mark Adams is VP of Advanced Power Marketing at CUI.
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