Smart buffers reduce complexity

Smart buffers reduce complexity

New Products |
By Jean-Pierre Joosting

The ZL40250-ZL40253 miSmartBuffer family is differentiated from industry traditional fanout buffers with compelling features including generating multiple frequencies using per output dividers. Also, the outputs of miSmartBuffers can be configured to generate native signal types such as LVDS, LVPECL, HCSL, HSTL and CMOS, allowing the devices to easily interface to other components on the board with no need for level shifters or termination components.

In addition, the devices’ outputs are grouped in six output supply voltage banks with CMOS output voltages from 1.5 V to 3.3 V, eliminating the need for multiple regulators and simplifying the design. The three, six or 10-differential output programmable fanout buffers’ per output control provides designers with flexibility to control signals as well as the ability to create factory pre-programmed devices to ensure clock availability and proper system bring-up for different applications.

“The introduction of our new miSmartBuffer devices provide a competitive advantage to Microsemi’s robust clock management buffer portfolio and enhances our reach within the communications, enterprise and data center markets,” said Maamoun Seido, vice president and business unit manager of Microsemi’s timing products. “The unique feature set of these devices and the ability to configure their outputs enabling designers to create larger clock trees when combining these buffers with Microsemi’s miClockSynth™ clock synthesizers or simplify small clock trees with a single miSmartBuffer, leading to significant cost savings.”

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