SMIC to report Tunnel-FET extension to CMOS

SMIC to report Tunnel-FET extension to CMOS

Technology News |
By eeNews Europe

Because of the low voltage operation SMIC (Shanghai, China) is declaring that the platform has potential for ultra low power applications such as the Internet of Things (IoT).

The details are due to be revealed at the upcoming International Electron Devices Meeting (IEDM) scheduled to take place at the Washington D.C. Hilton Hotel from December 7 to 9, 2015.

Although the minimum geometry of the process is not revealed in the abstract of the paper, it is one of the more interesting IEDM papers because of suggestions that a TFET process could be relatively near to deployment. The paper was written by researchers from Peking University and SMIC.

The TFET is usually thought of as an emerging potential device for use for sensor nodes and near-threshold computing at 5nm and beyond, when conventional electron transport devices run out of steam.

However, the paper will examine the variability C-TFETs with a view to high-volume production and SMIC stresses in the abstract that the complementary TFETs were made under in a standard 300mm wafer fab used for CMOS foundry business. The paper, in session 22 on steep-slope transistors, is entitled First Foundry Platform of Complementary Tunnel-FETs in CMOS Baseline Technology for Ultralow-Power IoT Applications: Manufacturability, Variability and Technology Roadmap.

As the TFET name suggests electrons use quantum tunneling – rather than thermal injection – to enter into the conduction channel. However, such devices have been very much associated with research rather than development with outstanding issues around the materials of choice and whether lateral or vertical structures are preferable.

Both III-V materials and silicon, germanium mixes have been the subject of TFET research. SMIC does disclose that it has demonstrated the use of a silicon-based TFET inverter as part of an electrical isolation regime required between neighboring devices. It also clams that an abrupt tunnel junction has been achieved allowing monolithic integration of C-TFET with CMOS.

The abstract adds that by use of a novel TFET device design improved performance and reduced variability have both been achieved with circuit level implantation showing a near doubling of performance and energy reduction of 66 percent at a VDD of 0.4V along with suppressed variation.

Related links and articles:

IEDM session on steep slope transistors

News articles:

TSMC turns logic FinFET into ReRAM

Quantum transistor harnesses new effect

Image sensors get seven papers at IEDM 2015

MEMS, sensors get four sessions at IEDM 2015

European research project aims to develop TFET process

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