SoC analysis tool steps up capabilities, adds ‘any CPU’ feature

SoC analysis tool steps up capabilities, adds ‘any CPU’ feature

New Products |
By Graham Prophet

Extended support includes improved performance monitoring and system optimization capabilities, enhanced integration with third-party tool-chains, improved support for functional safety applications, and General Availability (GA) of new analytics and communications IP.


As the cost of developing complex SoCs continues to rise, and the business risks from schedule slippage become larger, the company says, the advent of emulation and prototyping platforms has eased pre-silicon tasks, but post-silicon verification and optimization remains a major challenge for the industry. UltraSoc aims to address this challenge.

Many of the new capabilities and features are in software and tools – particularly in interfacing and supporting standard development environments. Specifically:

– Richer support for analytics and visualization, leading to the use of “Big Data” techniques for debugging and development

– Added tools and analysis capabilities to assist in performance monitoring and system optimization

– Enhanced support for developers using Python scripts to interact with UltraSoC IP for post-processing, analytics and visualization

– Migration to Eclipse version 4.5 (“Mars”) with the capabilities that come from an industry standard IDE

– Support for the GDB industry standard open-source debugger

– Direct integration with Lauterbach’s industry standard TRACE32 development environment

– Direct integration with the new version of CEVA’s toolchain for CEVA DSP


Additional hardware and semiconductor IP capabilities include:

– Enhanced Processor Analytic Modules to interface to MIPS and CEVA cores for debugging, trace and run-control. These complement the existing ARM and Xtensa core support

– Capability to support other cores, including the open-source RISC V core

– Support for ECC, parity and check sum logic, important for high-reliability systems. This is a key part of UltraSoC’s capabilities to support functional safety, automotive and ISO26262

– General availability of the new Universal Streaming Communicator (USC) that enables a variety of interface and communication systems to the SoC, including serial wire debug style communication and a high speed SerDes interface


UltraSoC’s suite of silicon IP is intended to allow designers to create an on-chip infrastructure that non-intrusively monitors the digital aspects of the chip’s behaviour – both hardware and software. The engineering team can gain a much more intimate understanding of the often complex interactions between diverse on-chip processor blocks, custom logic, and system software. These capabilities are valuable both in development and in-field, when they can be used to spot unexpected behaviour caused by bugs or by malicious interference, and to analyze performance trends.





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