SoC supports high speed data acquisition

SoC supports high speed data acquisition

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By eeNews Europe

For markets that require high-speed data generation and acquisition, and to make it easier to get a direct connection to the analogue-to-digital-converter (ADC)/digital-to-analogue-converter (DAC) and analogue front end (AFE), Texas Instruments offers the highly integrated KeyStone-based 66AK2L06 System-on-Chip (SoC) solution.

The 66AK2L06 SoC integrates the JESD204B interface standard, reducing the overall board footprint by up to 66%. This integration also allows designers in markets such as avionics, defence, medical, and test and measurement to develop products with increased performance and up to 50% lower power. TI cites DSP programmability and pre-validation of multiple high speed ADCs, DACs and AFEs. TI’s system level solution is further enabled on the 66AK2L06 SoC by the Multicore Software Development Kit (MCSDK) and RF Software Development Kit (RFSDK).

Extending TI’s highly integrated and scalable KeyStone multicore architecture, the 66AK2L06 SoC integration of a Digital Front End (DFE)/Digital Down Converter-Up Converter (DDUC) and a JESD204B interface delivers a reduction in system cost and power. The integration of TI’s DSPs and ARM Cortex processors, claims twice the performance of current competing solutions with software programmability. Four TMS320C66x DSP cores, each rated at up to 1.2 GHz of signal processing, allow users flexibility in programming via floating point. In order to perform complex control code processing, dual ARM Cortex-A15 MPCore processors deliver up to 1.2 GHz of processing power and enable real-time direct access to I/Os with low latency.

A Fast Fourier Transform Coprocessor (FFTC) module is accessible across all the DSP cores to accelerate the FFT and IFFT computations that are required in applications such as radar systems. Additionally, the network coprocessor (NETCP), a hardware accelerator that processes data packets with a main focus on processing Ethernet packets, has four gigabit Ethernet (GbE) modules to send and receive packets from an IEEE 802.3 compliant network, as well as a packet accelerator (PA) to perform packet classification operations such as header matching, and packet modification operations and a security accelerator (SA) to encrypt and decrypt data packets.

The adaptive power technology in 66AK2L06 provides up to 50% lower power than competing devices with cooling requirements. With integrated wideband sample rate conversion and digital filtering up to 48-channels, the 66AK2L06 eliminates the need for an additional device, thus reducing the board area by up to 66%.

TI further claims that designers can develop three times faster than with FPGAs or with competing solutions. With the 66AK2L06 SoC, developers have the ability to change DFE configurations on the fly after deployment through software, while storing multiple configurations in DDR or flash memory with the ability to switch dynamically. The integration of the DFE and JESD204B interface allows users to change filters to make optimisations through software programmability in days rather than weeks as required today with an FPGA.

JESD204B is a highly efficient, industry-standard serial communications link that simplifies the digital data interface between data converters and processors in high-speed applications, such as test and measurement, medical, defense and avionics. In addition to the 66AK2L06 SoC, TI’s JESD204B portfolio includes high-speed ADCs and DACs, and clocking products.

Building on the KeyStone-based MCSDK and RFSDK, the 66AK2L06 SoC enables developers to accelerate time to market by providing an out-of-the-box solution. TI’s development tools and runtime software support make migration and development for the multicore ARM platform simpler than ever. The MCSDK provides support for open source Linux and TI’s SYS/BIOS operating system for ARM cores. Evaluation modules (EVMs) will be available with the MCSDK and RFSDK with preloaded example projects. The MCSDK and RFSDK are shipped together with an XEVMK2LX EVM. TI Designs enable customers currently using an FPGA to connect data converters to signal processors to reduce cost with a direct JESD204B interconnection and the broad ecosystem offers additional resources that aid customers with hardware, software and new feature development needs.

TI; more information;

JESD204B and Synthetic Aperture Radar (SAR) whitepaper

66AK2L06 data sheet and product bulletin

66AK2L06 product video

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