Software tool allows analog IC design for reliability
Based on the proven Spectre Accelerated Parallel Simulator (APS) and the Virtuoso custom IC design platform, the Legato Reliability solution integrates the various capabilities into an intuitive cockpit. The solution addresses reliability aspects in all three phases of the product life cycle:
- Analog Fault Analysis – This can speed up analog fault simulation by a factor of up to 100, reduce test costs and avoid undetected production faults, which are the main cause of premature failure of IC designs.
- Electrothermal analysis – The developer can thus avoid thermal overload and thus reduce early failures during the service life of the product.
- Advanced Aging Analysis – This allows accurate prediction of product wear due to temperature and process variations.
“As electronics is a key element in many application-critical applications, designing chips has become a huge challenge as they must meet the requirements throughout the entire product lifecycle,” said Tom Beckley, senior vice president of Cadence and general manager of the Custom IC and PCB Group.
“Developers must keep the complete life cycle in mind during development. This includes avoiding undetected faults that can lead to field failures at the beginning of the life cycle and preventing thermal overload during operation under extreme conditions, such as in the engine compartment of a car or for a service life of more than 15 years”. The new Legato Reliability solution allows developers to answer these critical questions much earlier in the design process, Beckley said.
Legato Reliability also includes a dynamic electrothermal simulation engine. In automotive designs, there is a significant increase in temperature during normal operation due to the losses on the chip and in the power electronics. In addition, these components must also function under difficult ambient conditions in the engine compartment of a car. The combination of high power dissipation with a high ambient temperature can result in a thermal overload which leads to premature failures in normal operation. Using a dynamic electrothermal simulation, developers can simulate the temperature increase on the chip and validate the function of the temperature protection circuits.
As a component of the new software, Cadence also introduces a simulation engine that enables a new test methodology for analog ICs: Error-oriented testing. This extends the testing possibilities far beyond what was previously only possible with functional and parametric tests. Defect-oriented tests enable developers to evaluate whether manufacturing defects occur that are not detected in production tests and later cause field failures. In addition, the wafer test can be optimized and the number of tests required to achieve the desired defect coverage can be reduced. This is achieved by eliminating overcoverage and reducing the number of tests by up to 30 percent. Customer experience with the tool shows that the error simulation can be accelerated by a factor of more than 100.
“Analog error simulation is becoming increasingly important for us in order to meet our customers’ expectations,” says Dieter Härle, Project Manager at Infineon Austria. “We tested the Legato Reliability solution and were able to speed up the simulation time by a factor of more than 100.” Now Infineon wants to integrate the software into its production process.