Software update lifts abstraction level for Altera FPGA design-in
Spectra-Q lists capabilities that include compile time improvements, versatile and fast-tracked design entry, and drop-in IP integration. Users can design and implement at higher levels of abstraction for significantly faster design cycles to meet the next generation of design opportunities.
"As FPGAs and SoCs deliver dramatically increased capabilities with multi-million logic element devices, support for hundreds of interface protocols, and new hardened functional blocks, the productivity of software design tools must scale at a much faster pace than just logic element counts," said Alex Grbic, senior director of Software and IP Marketing at Altera. "The Spectra-Q engine is a … combination of software technologies that dramatically accelerates the design process by reducing designs iterations, while continuing to deliver the industry’s fastest compile times."
The Spectra-Q engine features faster algorithms and allows for incremental design changes without needing to perform a full design compile The engine also features a hierarchical database that enables users to preserve placement and routing information of IP blocks while making changes in other parts of the design. This helps ensure stable designs, eliminates unnecessary timing closure efforts and reduces compile times. The new engine also includes a common high-level design compiler for better quality of results and tighter integration between the Quartus II software and a variety of different front-end tools.
BluePrint Platform Designer
Built on top of the Spectra-Q engine is a platform design tool called BluePrint that allows designers to perform architectural exploration and assign interfaces with greater efficiency. The tool reduces design iterations by a claimed order of magnitude by allowing designers to explore and create legal IO placements up-front with real-time fitter-checking. The tool also includes a clock and core planning feature that greatly reduces the number of design iterations needed for timing closure.
Versatile and Fast-tracked Design Entry
The new Spectra-Q engine also fast tracks design entry for software, hardware and DSP designers. With multiple versatile design flows, designers can target FPGAs with greater efficiency in the language or design environment they prefer. In addition to providing support for the latest HDL languages, the new engine is designed to support Altera’s A++ Compiler for HLS (high level synthesis) to create IP cores from C or C++ which significantly boosts productivity through faster simulation and IP generation.
Quartus-II Software and IP Version 15.0 Released
Altera has released its Quartus II software version 15.0 which introduces new Hybrid Memory Cube and HDMI 2.0 MegaCores for the company’s Arria 10 FPGAs and SoCs. The portfolio also includes an upgrade in features and device support for the company’s JESD204B core to update Arria V support to 9.255Gbps as well as Cyclone V support up to 5 Gbps. IP debug toolkits for external memory interfaces (EMIF) and PCI Express are also available to help designers rapidly prototype and expedite qualifications with additional access points to perform test and debug on IP cores.
Altera; www.altera.com/spectraq
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