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SOI group moves on mobile front

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By eeNews Europe


The consortium members-ARM, Globalfoundries, IBM, STMicroelectronics, Soitec, and CEA-Leti—have announced results of an assessment and characterization of FD-SOI, saying that the technology is viable for mobile and consumer devices at the 20-nm node and perhaps beyond. The group has demonstrated the benefits of planar FD-SOI technology for these applications based on an ARM processor.

FD-SOI is one of several options competing for the next-generation transistor structure. At present, leading-edge chip makers are using conventional bulk CMOS and planar transistor structures for the 32-/28-nm nodes.

AMD, IBM and others are also using another type of SOI technology-partially depleted SOI-for their respective processors. In contrast, Intel Corp. has dismissed SOI, saying that it does not require the technology.

For 22- and 16-nm, there are a number of transistor candidates on the table: III-V, bulk CMOS, FinFET, FD-SOI, multi-gate, among others. So far, there are no clear winners.

Mark Bohr, Intel Senior Fellow and director of process architecture and integration at Intel Corp., recently said the chip giant is evaluating extremely-thin SOI, sometimes called FD-SOI. One source even thinks Intel is looking at rival tri-gate structures at 22- or at 15-nm. Bohr declined to elaborate on Intel’s directions.

In a recent interview, Gary Patton, vice president of the Semiconductor Research and Development Center at IBM Corp., said FD-SOI is a strong candidate for the 22-nm node. Some of the big silicon foundries-Globalfoundries, Samsung and TSMC-have dropped hints that they will push bulk CMOS silicon for the 20-nm node due to cost.

But many high-performance applications may also require FD-SOI. SOI refers to the use of a layered silicon-insulator-silicon substrate in IC manufacturing, which is said to reduce parasitic device capacitance and improve performance.

In FD-SOI, the top silicon layer is between 5- to 20-nm thick. ”Silicon under the gate is so thin that it is fully depleted of mobile charges,’’ according to Soitec, in a newsletter. ”There is no floating body effect.’’

In partially depleted SOI, the top layer is between 50- to 90-nm thick. Silicon under the channel is partially depleted of mobile charge. This in turn can ”lead to charges accumulating in the quasi-neutral region,’’ which can cause the floating-body affect.

One of the issues for SOI is whether it’s suited for the mobile market; there are concerns about the scalability and so-called ”history effect.’’ For years, SOI has been used in desktop processors and other high-performance applications.

Now, the SOI crowd is pushing the technology for mobile applicatons. At last year’s Semicon West trade show, SOI substrate specialist Soitec Group (Paris) said the company was readying its Ultra-Thin Buried Oxide (UTBOX) extension to its Ultra-Thin (UT) silicon-on-insulator (SOI) platform-or FD-SOI-for mobile consumer devices.

With ultra-thin top silicon thickness variation within a +/- 0.5nm maximum range, and a buried oxide layer as thin as 10-nm, these wafers are in full compliance with customer requirements, according to Soitec. High-volume capacity has been available for the 22-nm node at Soitec’s manufacturing sites in France and Singapore.

In 2008, IBM Corp.’s Microelectronics Group rolled out what it claims is the industry’s first 45-nm, silicon-on-insulator (SOI) foundry offering. It’s unclear if IBM will offer the same service for FD-SOI.

Meanwhile, it’s possible that Soitec jumped the gun on last year’s announcement at Semicon. It’s still unclear if chip makers will jump on FD-SOI or not for the next nodes. Perhaps chip makers remain worried about the design considerations in the mobile space.

Now, the SOI Consortium is throwing its weight behind FD-SOI for mobile. “FD-SOI is a great option to improve the key metrics for mobile markets: power, frequency, manufacturability and most importantly cost efficiency,” said Horacio Mendez, executive director of the SOI Industry Consortium. FD-SOI is scalable, fully compatible with bulk silicon and can be manufactured with no ”history effect,’’ he added.

Early benchmarks on FD-SOI technology demonstrate the ability to reduce the SRAM operating voltage by 100-150mV, thereby reducing memory power consumption up to 40 percent while maintaining the stability of the SRAM, according to the consortium.

Traditionally, low power manufacturing technology processes from one generation node to another yield a performance gain ranging from 20 percent to 30 percent. This assessment indicates that when the same transition also includes FD-SOI technology an additional 80 percent gain can be achieved beyond the traditional increase, according to the group.

Due to its advanced starting substrate, FD-SOI wafer processing is simpler for the chip manufacturer. The elimination of a considerable number of mask layers during transistor-formation processing drives simpler manufacturing process flow, and thereby a cost efficient approach to further shrinking CMOS transistors, according to the group.


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