SOI-technology, monolithic RF chip optimises Doherty amplifier performance

SOI-technology, monolithic RF chip optimises Doherty amplifier performance

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By eeNews Europe

Through a digital interface, MPAC enables alignment of the phase and amplitude between the Doherty amplifier’s carrier and peaking paths. Designed for wireless infrastructure applications, MPAC improves system performance, lowers costs, increases reliability and provides maximum tuning flexibility.

“Doherty architectures have long encountered difficulties in optimising performance, which leads to higher manufacturing and engineering costs,” says Duncan Pilgrim, Peregrine’s vice president of marketing. “MPAC provides an ideal solution for this RF challenge and does so monolithically through intelligent integration—something gallium arsenide (GaAs) technologies could never achieve. Peregrine is introducing a superior UltraCMOS product that will disrupt GaAs-based alternatives.”

Pilgrim’s assertion is the the MPAC makes the Doherty amp easier to design, and makes it work better. The Doherty configuration attempts to amplify the high peak-to-average signal of today’s modulation schemes efficiently by splitting the signal into two paths; one amplifier handles the “base” of the signal – effectively, the carrier – while the other is appropriately termed the “peaking” amplifier. Implemented as intended, this can improve power efficiency (RF power added relative to DC power consumed) but the phase and amplitude between the two paths must be matched exactly – today, this is a matter of high-cost, low tolerance passive components and manual tuning, with no option to correct the setup as conditions (such as temperature) change, or components age.

While widely used in the wireless infrastructure industry, Doherty amplifiers require a considerable engineering investment to manually implement and optimise. Any mismatch or misalignment in phase and amplitude between the Doherty architecture’s carrier and peaking paths can quickly contribute to higher costs and degradation of the system’s overall performance. Even after optimising with discrete components, the system remains inflexible to manufacturing variances from power amplifier assemblies.

MPAC solves this engineering challenge with the industry’s first monolithic solution to maximise asymmetric and symmetric Doherty amplifier performance. MPAC also integrates Peregrine’s industry-leading digital step attenuators and phase shifter products onto a single die.

On an UltraCMOS (silicon-on-insulator, SOI technology) chip, each MPAC product includes:

90-degree hybrid splitter

Two phase shifters

Two amplitude controllers

Digital SPI interface

MPAC offers RF engineers improved system performance, lower costs, increased reliability and maximum tuning flexibility for either LDMOS (laterally diffused metal oxide semiconductor) or GaN (gallium nitride) based Doherty power amplifier architectures. MPAC performance advantages include improvements in power added efficiency, linearity across the frequency range, Doherty bandwidth through better matching and effectiveness of the digital pre-distortion (DPD) loop. MPAC reduces bill of materials (BOM) costs by eliminating the need for external components such as DC blocking capacitors and reducing component count for greater board area. It also lowers costs by providing tighter production distributions on expensive power amplifier assemblies. With uniformity and repeatability between transceiver paths, MPAC increases system reliability and increases transceiver yield. Finally, MPAC delivers improved flexibility with adjustable phase and amplitude tuning for each independent path through the SPI digital interface. This flexibility enables real-time adjustments in order to optimise for operational or environmental changes.

Pilgrim says that initial implementations using MPAC are likely to focus on setting up an amp at final test, but re-aliginig an amp at power-up; or periodically; or even in real time, are all possible.

With a wide positive and negative phase shift range and a fine step size, MPAC delivers high linearity of 65 dBm IIP3 and extremely low power consumption of 300 µA. It provides performance advantages in power handling and port-to-port isolation. UltraCMOS technology enables ESD performance of 1 kV, an extended temperature range up to 105C and a wide power supply range from 2.7 to 5.5V.

The first product in the MPAC family is the PE46120. Currently being sampled to select customers, the PE46120 covers a frequency range of 1.8 to 2.2 GHz. The MPAC product family plans to cover all cellular frequency bands with the PE46130, 2.4 to 2.8 GHz; PE46110, 0.7 to 1.0 GHz; and PE461xx, for LTE-A bands.

Pergrine Semiconductor;

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