Sondrel opens up IP library for licensing
UK chip design house Sondrel is licensing its in-house IP.
This starts with a suite of IP blocks for general SoC management to control start-up of devices, clock and reset control and power domain handling. The SoC Management Suite has three components – the PMU (Power Management Unit, the URG (Universal Reset Generator) and the UCG (Universal Clock Generator).
“For years, we have been creating IP blocks for our internal use when we design custom chips. We are now making these available for licensing by third parties,” said Oliver Jones, who took over at CEO last Friday. “They are silicon proven as we have already successfully used them in designs for our customers. We had to create these IP blocks as there was nothing commercially available to deliver the functions and performance that we required for the advanced ultra-complex custom chips that we design. Some are slightly unusual but that is the very reason why we created them. If we needed them for a design, then others will too.”
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The Power Management Unit (PMU) is used for managing the start-up of the SoC and bringing the SoC out of reset as well as providing software control to allow any switchable digital domains to be powered up and down. It provides software control over the reset tree once start-up is complete and manages system faults, including taking mitigating action as required and acting as the Error Detection Unit. It also generates the system response to functional safety faults detected in the system such as putting the system into safe mode.
The PMU can interact with a reset manager to control the resets via Sondrel’s Power Down Controller Interface control bus. This links to Universal Reset Generator (URG) IP that handles on-chip reset management.
The URG IP provides reset-tree management for the increasing complexity of logic within an SoC. A typical SoC would employ at least one URG IP instance, while a multi-power-domain SoC or implementation requiring more distributed reset control, could have multiple instances depending upon the reset tree management requirements. The goal is to have a single, generically configured block which will support the correct sequencing of resets to the whole system. These can come from hardware triggers or software events or from the PMU.
The UCG IP supports multiple clock sources and references as input to a generic crossbar with up to 128 clocking channels which can be independently software configured. There are clock dividers on each channel and a clock enable (glitch-free implementations) and observation clocking points as well as DFT (Design For Test) control of clock outputs. Safety mechanisms detect if a default clock has failed and indicating the fault to the system.
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