Spanish startup performs RISC-V open core surgery

Spanish startup performs RISC-V open core surgery

Interviews |
By Nick Flaherty

Spanish startup SemiDynamics has developed fully configurable 64bit RISC-V processor IP for high performance chip designs in AI, Machine Learning (ML) and High-Performance Computing (HPC).

The customisable cores are process agnostic with versions already being supplied down to 5nm and use a new architecture for memory management, SemiDynamics CEO and founder, Roger Espasa tells eeNews Europe.

“The change to RISC-V is driven by the customer need to be able to change the silicon rather than a cost play,” Espasa tells Nick Flaherty. “What they are looking for is inventing instructions, adding something to the core to justify their investment in silicon. You don’t do it to plug and play a few IP cores. It’s for a secret sauce that solves a problem in the market.”

The company was established in 2016 and has worked on several high performance massively multicore designs.

“We have an HPC background and we know what it takes to move a lot of data so we have a lot of knowledge in AI and HPC to help customers all over the place, not just in HPC. We do that by being willing to do open core surgery on our cores, customising for their problem,” he said.

“We enjoy taking our knowledge on high performance cores where our customers realise that caches are not solving their problems. We have a customer with an AI design at 5nm with vector units and we also have a customer for packet processing with high frequency processing with over 50 instructions to be added to the core.”

The first core in the family is Atrevido, with 64-bit native data path and 48-bit physical address paths, Out-of-Order scheduling and the Gazzillion technology to handle highly sparse data with long latencies and with high bandwidth CXL memory systems that are typical of current machine learning applications. This adds tiny buffers in key places to ensure that the cache lines keep the core running at full speed rather than waiting for data.

The core can be configured from 2-way up to 4-way to help accelerate the portions of custom AI chips and is supplied with verification tools and artefacts.

“We are an IP company that puts the customer first, modifying the IP. We will not take requests to build a system that doesn’t include our IP, but we provide our cores, look at the interconnect then tailor it as a bespoke solution,” he said.

“Specialisation is good. We are really good on the architecture, understanding the customer needs and customisation, but we think it is better they find a supplier that can pull it all together.  

The company is aiming for organic growth from 30 to 45 people this summer, based in Barcelona, growing to 100 with engineers who may be in other regions by the end of the year.

“After the organic growth, the chiplet market is coming and I’m pretty sure we will be a player when that matures,” he said.

“Until now RISC-V processor cores had configurations that were fixed by the vendor or had a very limited number of configurable options such as cache size, address bus size, interfaces and a few other control parameters. Our IP cores enable the customer to have total control over the configuration be it new instructions, separate address spaces, new memory accessing capabilities, etc. This means that we can precisely tailor a core to meet each project’s needs so there are no unrequired overheads or compromises,” he said.

“We have the fastest cores on the market for moving large amounts of data with a cache line per clock at high frequencies even when the data does not fit in the cache. And we can do that at frequencies up to 2.4 GHz on the right node. The rest of the market averages about a cache line every many, many cycles, that is nowhere near our one every cycle. So, if the application streams a lot of data and/or the application touches very large data that does not fit in cache, we have the best RISC-V cores on the market.”

The core includes memory management unit (MMU) support to run Linux in cache-coherent, multi-processing environments with two to hundreds of cores. It is vector ready, supporting both the RISC-V Vector Specification 1.0 as well as the upcoming SemiDynamics Open Vector Interface.

“When we do the customisation is we send a bitstream that runs in a Xilinx FPGA –  this is an absolute must. We have seen one case where that turned the technical debate into a funding debate as they went back to funders showing it was working,” said Espasa.


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