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Spectre calibrates SPICE models for cryogenic memory

Spectre calibrates SPICE models for cryogenic memory

Technology News |
By Nick Flaherty



Semiwise and sureCore in the UK have used the Spectre tool from Cadence Design Systems to overcome critical challenges in developing cryogenic CMOS circuits for quantum computer systems.

The cryogenic memory collaboration saw the successful modification of transistor models on GlobalFoundries 22FDX using the Cadence Spectre Simulation Platform for analog, mixed-signal, and digital circuit simulation and verification at cryogenic temperatures.

This was part of the Innovate UK project for the Development of CryoCMOS to Enable the Next Generation of Scalable Quantum Computers, where Semiwise in Scotland developed the first robust transistor SPICE models designed to function in extreme cryogenic environments. This advancement is pivotal for quantum computing, drastically increasing the potential number of qubits within a system and significantly expanding the computational capabilities necessary for tackling complex, real-life problems.

“We were able to develop production-worthy designs for cryogenic CMOS circuits by using cryogenic transistor measurements performed by Incize in conjunction with a leading commercial TCAD simulator. This allowed us to create PDK-quality compact transistor models that include corners and mismatch,” said Professor Asen Asenov, CEO of Semiwise.

The project used low power SRAM cells from SureCore that can operate from 77K (-196°C) down to the near absolute zero temperatures needed by quantum computer systems. Both standard cell and IO cell libraries have been re-characterised for operation at cryogenic temperatures for an industry standard RTL to GDSII physical design flow to be readily adopted.

“The critical storage element, the bit cell, must essentially be treated as an analog circuit that is very sensitive to process variability and mismatch. When we develop new memory designs and their associated compilers, we need to run thousands of statistical circuit simulations to guarantee the yield and reliability of our IP,” said sureCore CEO Paul Wells.

“We are excited to work with Semiwise and sureCore in developing models in the Spectre Simulation Platform for use on cryogenic CMOS circuits,” said Tom Beckley, senior vice president and general manager, Custom IC & PCB Group, Cadence. “We are delighted that the Spectre Simulation Platform now has calibrated SPICE models for cryogenic environments.”

The first 22FDX SRAM cryogenic memory tapeout by sureCore to validate both recharacterized standard cells and a range of embedded memory IP is currently in the fab. Agile Analog in Cambridge and Siemens EDA were also involved in the project. 

www.semiwise.com; www.surecore.com; www.cadence.com

 

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