Speed-power gains of alternative transistor technology shown in ARM core
Asked why, given the vast resources that have been poured into semiconductor device development over many years, it should fall to a third-party IP company to offer a power-saving innovation in something so fundamental as the basic transistor, a SuVolta spokesman offered a simple explanation. Almost all [conventional] device development has been fundamentally aimed at increasing performance, and low-power variants have been derived from those devices. SuVolta says its approach has been to carry out basic transistor development with low-power as the primary aim. You can trade-off that gain to see faster speeds at equivalent power, the company adds.
Now, the company says that its claims have been validated by with Fujitsu’s implementation of an ARM processor core in 65-nm technology using its transistors, yielding significant processor speed gains with associated power reduction in a Cortex-M0 processor. The ARM Cortex-M series processor was manufactured with SuVolta’s Deeply Depleted Channel (DDC) technology on a 65nm bulk planar CMOS DDC process. With SuVolta’s transistor technology, designers are able to significantly reduce power or dramatically improve performance, depending upon design requirements.
When compared to an identical ARM Cortex-M0 processor manufactured in the conventional 65nm process, with a 1.2V supply voltage, the DDC transistor-based ARM implementation operating at 0.9V demonstrates the following benefits:
50% lower total power consumption at matched 350 MHz operating speed.
35% increased operating speed (performance) at matched power.
55% increased operating speed when operated at matched supply voltage.
“We’ve now validated the benefits of the DDC technology in a complex SoC, by combining the ARM Cortex-M0 CPUs with SRAM instances and various analogue components,” explained David Kidd, senior director, digital design at SuVolta. “The results speak for themselves – power-performance optimized CPU cores, with results that hold across process corners and temperature, plus, SRAMs with 150 mV lower minimum operating voltage, 50% less leakage power at matched SRAM read current, and more than 5x less leakage power in retention mode.”
The company adds that the transistors also offer gains for analogue circuitry, as lower leakage means better matching between transistor pairs; the structure also reduces manufacturing “spread” in the process, and the slowest/fastest devices from a batch covnerge.
The technology is reported to scale well with reducing geometry; SuVolta has also announced joint development of a 28-nm process with foundry UMC. At this stage in its development, SuVolta claims six major engagements, the majority of which it will not yet name but which it says are all “major players”. However, the technology could also serve smaller companies such as fabless semiconductor suppliers, or ASIC designers – the DDC transistor could remove the need for a design to migrate to a smaller process node to reduce power, for example.
The DDC transistor structure allows designers to use multiple threshold-voltage (VT) transistors on a die across, offering the strategy of replacing only the “leakiest” devices in a design – and the SRAM cells – for a most-return-for-least-effort approach, or of using the DDC device across the entire design. The former (“DesignBoost”) can yield 40-50% reduction in leakage power: the latter (“PowerShrink”) may deliver 50-60% lower leakage power and 30-50% lower active power. It is compatible with existing processes and EDA tool sets, the company says.
The Fujitsu Cortest M0 core was a 350 MHz design using 8 mW at 1.1V; with the DDC technology it will run at 0.9V, 350 MHz and use 4 mW; or stay at 1.1V /8 mW and run 35% faster; or run at 1.2V and 11 mW at around 55 MHz. These operating points are all on the same build, without re-optimising.
UMC’s announcement concerns its 28nm high-K/metal gate process that implements SuVolta’s DDC technology to target mobile applications. The Taiwanese foundry has integrated SuVolta’s DDC technology into its 28nm High-K Metal Gate (HKMG) high-performance mobile (HPM) process. It will offer both “DDC PowerShrink low-power platform” and “DDC DesignBoost transistor swap” options. According to T.R. Yew, vice president of Advanced Technology Division at UMC, “By incorporating SuVolta’s advanced technology into our HKMG process, we intend to deliver a 28nm mobile computing process platform to complement our existing Poly-SiON and HKMG technologies.”
SuVolta; www.suvolta.com
In the diagram of the DDC transistor above;
Region 1 is the Undoped/lightly doped region leading to;
– Improved matching
– Superior scalability
– Higher speed at lower VDD
Region 2 is the VT setting offset region, allowing;
– Multiple VT on chip
Region 3 is the Screening region, delivering;
– Improved yield
– Strong body coefficient (tighter corners)
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