Spirent, Cadence team on networking chip pre-silicon verification
UK test house Spirent Communications is working with Cadence Design Systems on networking system-on-chip (SoC) verification that bridges the gap between pre-silicon and post-silicon verification.
The collaboration brings sophisticated virtual Ethernet traffic emulation and testing capabilities to pre-silicon verification in the Cadence Palladium Z2 Enterprise Emulation and Protium X2 Enterprise Prototyping systems.
The combination with the Spirent TestCentre provides the capacity to emulate any port speed from 1G to 800G at the application level and the ability to quickly introduce additional features to enable new use cases as required.
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“Our collaboration with Cadence provides access to the latest Chip Design Verification solution to help customers identify critical problems early in the design lifecycle and accelerate time to market for the latest innovations driving the industry,” said Aniket Khosla, VP of product management for Cloud and IP at Spirent. “It will help reduce development time, simplify testing of the complex Ethernet chipset design process, and ensure that new products perform as expected.”
Michael Young, senior product management group director, System and Verification Group at Cadence said: “Through our work with Spirent, Cadence is continuing our commitment to work with industry leaders to bring best-in-class solutions to the pre-silicon verification market. When integrated into the Palladium emulation and Protium prototyping systems, Spirent’s’ Ethernet traffic emulation and test capabilities allow mutual customers to extend their verification with real-world traffic and scenarios, greatly reducing time to market.”
The comprehensive integration of the test application and emulation environment avoids the need for external test hardware with cost savings from identifying and fixing issues in early-stage chip design. A unified test platform that bridges gaps between pre- and post-silicon verification, enabling continuity of testing from the earliest phases of product development through customer deployment
The test and emulation system has the capability to test all phases of silicon product lifecycle, time-saving application re-utilization, implementation of standard metrics for more effective measurement and result analysis and easier integration into CI/CD workflows.
“Chip design is time-intensive, testing early at the pre-silicon design phase helps speed up time to market for the latest industry innovations by reducing issues and risks later in the development cycle” says Khosla. “The new unified test platform reduces testing complexity and accelerates the technology design and development of Ethernet chipsets.”
www.cadence.com; www.spirent.com
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