ST heads back into silicon photonics with mass production at Crolles
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STMicroelectronics has developed a silicon photonics technology for next generation 800Gb/s and 1.6Tb/s optical modules in data centres.
The PIC100 silicon photonics (SiPHo) process on 300mm wafers at Crolles in France can integrate multiple complex components into a single chip, while ST’s next generation proprietary BiCMOS technology brings ultra high-speed and low power processing alongside.
This is being driven by the AI boom for both rack interconnect and chip-to-chip links, says Vincent Fraisse, general manager for the RF and optical communications sub-group at STMicroelectronics.
“In the new era of AI servers with all elements optically interconnected, ST has the technology for datacentre challenges for higher performance and greater energy efficiency for the power supply and the interconnect,“ he said. “The AI boom pushes the need for better performance and more important better power efficiency in data centres.“
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The company is entering mass production of silicon photonic devices at Crolles in France on 300mm wafers with yields comparable to that of digital devices.
“We believe we have the best BiCMOS technology for the electro integrated circuits (EIC) but more importnantly most designs are moving to silicon photonics. This allows longer range at higher speed, potentially even eating into short range copper. This performance gain can be use for power advantages to provide a better signal to remove the DSP and save power.“
“We decided to hold as the market was not ready but now we believe it is. We believe this is the only 300mm technology with 200Gbit/s per lane. We can attach fibre to the edge of PIC for less losses and easier integration for both co-packaged and pluggable modules,“ said Fraisse.
“This represents the first step for our PIC product-family and, thanks to close collaboration with key partners across the entire value chain, our ambition is to become a key supplier of silicon photonics and BiCMOS wafers for the datacenter and AI cluster market, be it pluggable optics today or optical I/O tomorrow,” said Remi El-Ouazzane, President, Microcontrollers, Digital ICs and RF products Group at STMicroelectronics.
A key customer in the development is Amazon Web Services (AWS), which has its own AI training and inference chips. “AWS has been intimately involved in the development of the silicon photonics and we also have a cooperation with the leading supplier of optical modules for 1.6Tbit/s systems,“ said Fraisse.
“PIC100 will enable interconnection between any workload including Artificial Intelligence (AI). AWS is working with STMicroelectronics based on their demonstrated capability to make PIC100 a leading SiPho technology for the optical and AI market.” said Nafea Bshara, Vice President and Distinguished Engineer at Amazon Web Services.
There is another market coming for SiPho which is chip to chip interconnect. This is a key area for startups such as Celestial AI and Lightmatter.
“ST will provide all the tools to build these optical I/Os within the PIC100 design platform,“ he said.
The BiCMOS for the EIC devices uses the B55 and B55x silicon germanium (SiGe) process developed as part of the SHIFT project for RF devices and is now being used for a 200 Gbit/s/lane transimpedance amplifier (TIA).
“We have 20 large scale customers designing EICs and getting more and more traction. We can handle the entire value of the supply chain from the chip design, assembly and electrooptic testing which will be a valuable offering to our customers,“ he said.
The PIC100 process on an SOI substrate has a 50GHz bandwidth with silicon and silicon nitride (SiN) waveguides, SiGe diodes with a thick core to couple the fibre to the edge of a chip with low losses.
“We are bringing the optical interconnect as close as possible to the GPU. You would connect the SERDES to an optical I/O engine built of the EIC and modulated by the PIC and connected to the fibre. The laser is external and built with III-V technology and coupled to the PIC.”
A process development kit (PDK) for PIC100 will help chip developers use the technology. “There is a PDK open to all out customers based on devices we have developed at ST with a reference modulator, photodiodes, waveguides, mux and demux, but we will also support customisation of the different devices,” said Fraisse. “What is important for us is the yield and reliability for the solution to be viable in an AI cluster.“
The PIC technology will ramp up this year in H2 2025. “We see 200Gbit/s/lane ramping now and one can see that new generations are coming every two years and we have seen a big acceleration so I would expect 400Gbit/s per lane in two years in significant deployment in infrastructure,“ he said.
“This is the right time for ST to introduce new power efficient silicon photonics technology and complementing it with a new generation of BiCMOS for our customers to design the next wave of optical interconnect products, which will enable 800Git/s and 1.6Tbit/s solutions for the hyperscalers,” said El-Ouazzane.
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