STMicroelectronics is developing a process technology that will combine microcontrollers with gallium nitride (GaN) in a single chip.
This is built on the Bipolar-CMOS-DMOS (BCD) technology where ST has been awarded an IEEE Milestone for the development of the technology.
The BCD development started 35 years ago, combining analogue, logic, memory and power in a 4micron process on 4in wafers. The 10th generation soon to begin production on a 90nm process and this will lead to a 40nm process with highly integrated microcontrollers for wired and wireless charging devices and many other power applications.
“The roadmap is increasing digital processing and higher power and voltage, with process customisation,” said Guiseppe Croce, smart power technology R&D general manager at ST.
The current generation uses a 90nm process with phase change non-volatile memory. “The development on the following generation is based on 40nm proprietary technology for our microcontroller products but there are many challenges for integration, including the characterisation of the cross talk between the domains,” he said.
This is the 52nd IEEE milestone for the European region alongside Maxwell’s equations, Volta’s battery, Marconi’s wireless telegraphy in 1902, the Bletchley Park code cracking in the UK and the development of Public Key Cryptography in 1975.
ST has processed over 5m wafers in the 35 years of the technology, with over 40 billion chips produced, 3 billion of those in the last year, marking the acceleration of the adoption of the technology.
A further step is to add gallium nitride (GaN) high power technology to the BCD process. Drivers are already integrated on a monolithic single chip but the step to adding microcontrollers is a significant.
“Using alternative semiconductor materials such as wide bandgap materials are becoming mainstream with SiC leading. GaN architectures look promising for future monolithic power integration with increased efficiency and voltage,” said Orio Bellezza, president of technology, manufacturing and quality at ST.
“By combining the advantage of GaN with traditional silicon materials we can address a large number of applications. Integrated solutions have embedded coreless transformers on miniature BCD platforms but the challenge is the high voltage where 6KV isolation is a clear trend. Despite using dielectric layers major integration challenges are raised by the thickness of the layers required.”
“Smart power is still playing an important role,” he said. “There are two major challenges, The historical evolution creates major challenges in the scaling of the power and analogue stages. On the other side there is a cost optimisation challenge that has always been a key driver. Innovation will drive the evolution.”
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