ST restructures for the AI age

ST restructures for the AI age

Business news |
By Nick Flaherty

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STMicroelectronics is fundamentally restructuring its business for the AI age, introducing predictive qualification and fully automated IP, library, test and packaging.

ST aims to introduce new business structures and manufacturing and test strategies along with IP and chip designs in three quarters rather than two to three years using AI and digital twins.  

“We have a lot of IP and traditionally the way we created IP was 80% in silicon and 20% for the rest but that created a monster that was difficult to qualify,” said Fabio Gualandris, president of manufacturing, quality and technology at ST Microelectronics at the Leti Innovation Days this week in Grenoble, France.

This needs a new organisation, new process and IP characterisation and entirely new test and manufacturing processes, he says. The company is one year into the three year transformation.

“We have developed a different approach to partition the IP,  decide the silicon to use, and integrate the IP in a more holistic way. We need to master the performance of our IP regardless of the technology we select. Here we made a big change into predictive qualification.”

“In the past people developed predictive maintenance to anticipate a failure, and in the same was we go into the technology. This is a way to shorten time to market. To do technology we need a lot of capex, billions of dollars, and we need to anticipate the return on investment (ROI) as much as possible. The amount of money we need for semiconductors is impressive.”

“To develop the process, develop the tools and qualify the process typically took two to three years. Now the target is three quarters, and with the technology today that is not possible. We need to simulate the full design of the product using massive amounts of computing power.”

This needs a fundamental change to the way the company is structured, as well as the way process technology and chips are developed. It builds on projects building digital twins of its fabs to provide more flexible manufacturing and test as well as fully automated packaging.

“This is the big challenge in our workforce upscaling,” said Gualandris. “The only way to survive is to create an organisation that is future proof, and you either need to know the future or be very fast to understand and react, and you need to be smart, and to do that you need to create a network organisation.”

This is a ‘neuron organisation’ where each employee is a ‘neuron’ and the more contact a neuron has, the better for the organisation.

This also changes the way products are developed, which when the company has 34,000 products is significant. Now the company is driven by the product roadmap which drives the technology roadmap and leads to the product design kit with the process technologies and libraries, he says.

“We started this a year ago and to complete this it will take a couple of years, The integration of IP will be the final result of this approach,” said Gualandris.

This is also driving a completely new, fully automated test strategy.

“For many years testing has been regarded as important but now we have a complete new vision that is under development with partners but the key point is that to have an effective IP portioning needs a revolution in testing with full automation as there are a lot of operations that require different approaches,” said Gualandris.

It has developed a Virtual Test Library that uses AI to generate design IP libraries, cutting the development time from one year to three weeks. More AI will cut this even further.  

“We started three years ago on using AI to build test libraries. These are validated by an engineer now and in the future will be validated by another algorithm,” he said.

This automation strategy has already started in the packaging side of the business.

“We completely redefined the structure of the tools. Through the automation of material handling a factory in one to two years will have a totally different approach, you will not recognise the layout. To do this, we have to rethink many things, from System in Package (SiP), silicon and integration, passive active, wire, BGA, interposers, that’s the way to go.”

One of these moves is panel level packages, which the company introduced in its Malaysian packaging plant in 2022. The 700mm x 700mm 20kg panel holds 63,000 devices and the company ramped production from zero to 4m a day in 4 weeks, with a capacity up to 8m devices per day.

“The line is fully automated and we import a lot of technology from outside the semiconductor industry so we found partners outside traditional suppliers in food and automotive.”


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