ST starts shipments of its Stellar microcontrollers to selected customers

ST starts shipments of its Stellar microcontrollers to selected customers

Feature articles |
By Christoph Hammerschmidt

With the Stellar SR6 MCU family, which is scheduled to go into production in 2024, ST is primarily targeting developers in the vehicle body and powertrain sectors. The concept of domain or zone controllers enables more design flexibility, the shift of numerous functions from the software to the hardware level and higher system reliability. Incidentally, it simplifies the wiring loom in the vehicle.

The Stellar SR6 MCUs are implemented in ST’s FD-SOI process technology, which, according to the manufacturer, is characterised by excellent SER (Soft Error Rate) values – one of the prerequisites for ensuring the required high system reliability and availability for Functional Safety in applications according to ISO 26262 up to ASIL-D.

The building blocks provide hardware-based virtualisation so that multiple software applications can co-exist while maintaining performance and real-time determinism. At the same time, flexibility for designers is increased as multiple independent applications or virtual ECUs (Electronic Control Units) can run on the same physical microcontroller.

The first Stellar SR6 P and G series MCUs are equipped with up to 20 Mbytes of robust phase-change memory (PCM), which ensures a high level of performance and data preservation and meets AEC-Q100 Grade 0 requirements. The so-called dual-image storage of the Stellar series also allows efficient over-the-air reprogramming (OTA) with a significant reduction in memory requirements. This is made possible by the possibility of configuring a PCM cell structure with the aim of doubling the memory size during OTA updates up to 2 x 20 MByte. Access times are also shorter with PCM memory than with other non-volatile memories such as 1T (single transistor) NOR flash.

The Stellar SR6 MCU family consists of two series, P and G, but they are based on the same platform.

The Stellar P Integration MCUs are designed to meet the needs of next-generation powertrain and electrification integration/domain systems, and feature high real-time performance and determinism to deliver a superior driving experience and functional safety.

The Stellar G Integration MCUs bring efficient accelerators for protected data routing over CAN, LIN and Ethernet networks and feature a rich set of communication interfaces. With their flexible low-power modes, which support low quiescent current consumption, and an intelligent monitoring subsystem, the Stellar G microcontrollers guarantee optimum energy efficiency overall.

Each device is customised for its intended application to provide optimised, rational solutions for the requirements of the next generation of vehicles.

In terms of architecture, the Stellar SoCs are based on six Arm Cortex-R52 cores. To meet the requirements of the ISO 26262 safety standard, they are equipped with lockstep and split/lock capabilities. The Cortex-M4 cores are also joined by three Arm Cortex-M4 cores with floating-point arithmetic and DSP additions. A PCM memory is integrated on the chip, which is characterised not only by high performance but also by bit-level access possibilities. The latter should open up new possibilities in application design and prevent single-bit errors. A

hardware security module (HSM), which is also integrated, offers a complete implementation of the EVITA (E-safety Vehicle Intrusion Protected Applications) cyber protection architecture. The HSMs are combined with multi-bus routing to protect connectivity to time-sensitive vehicle networks (Ethernet, CAN-FD, LIN). In addition, the Stellar SoCs offer Special Encryption Accelerators for MACsec (Media Access Control security protocol), IPsec (IP security protocol suite) and CAN authentication.

Related articles:

Automotive microcontroller supports hardware virtualisation

STMicroelectronics joins Car Connectivity Consortium

Automotive electronics complexity at tipping point, study warns

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