ST, CAES team on octacore RISC-V space chip with selectable cores

ST, CAES team on octacore RISC-V space chip with selectable cores

Technology News |
By Nick Flaherty

Space system designer CAES is to design the first eight core fault tolerant chip that is selectable between different architectures, including RISC-V.

The radiation hardened GR765 System-on-Chip (SoC) will be the first user selectable CPU for space, allowing users to chose the legacy LEON5 SPARC V8 or the new NOEL-V RISC-V RV64 processor cores.

A single core test chip has been built in Europe on the 28nm FDSOI process technology from STMicroelectronics.

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“CAES is excited to announce the first user-selectable CPU for space. We are providing our customers with options to select the best architecture based on their requirements, while meeting the space industry’s future needs for more computing and a seamless ecosystem as well as addressing Size, Weight and Power (SWaP),” said Mike Elias, Senior Vice President and General Manager, Space Systems Division of CAES, which has multiple contracts with the European Space Agency (ESA) for the development of the chip.

CAES will work closely with STMicroelectronics on product manufacturing and qualifications for the GR765.

Based on the radiation test on the demo chip, CAES estimates the SEU tolerance for the GR765 product to be at least five times harder than the current radiation hardened processors. CAES will implement its legacy approach to fault tolerance, allowing software to transparently continue execution in presence of correctable errors, as well as extending fault tolerance to peripherals and software libraries.

The GR765 will allow the reuse of legacy LEON SPARC software or the development of new software for the NOEL-V RISC-V architecture, providing the option to use software and tools from other industries, including development tools from Ashling.

“We are proud to team with CAES on their next-generation microprocessors for space. The combination of proven SPARC and RISC-V technology with 28nm FDSOI’s technology capability and maturity for space is a perfect match,” said Francois Martin, Head of Space & Defense ASICs Business Development, Microcontroller & Digital Group, STMicroelectronics. “In addition to silicon manufacturing, ST provides HiRel product manufacturing and qualification through its trusted supply chain in its factories in Crolles and Rennes, France.”

The Advanced Research in Telecommunications Systems (ARTES) and Technology Development Element (TDE) programme contracts will enable CAES to move forward with the GR765 prototype development and manufacturing on this technology.

CAES previously received funding from the Swedish National Space Agency (SNSA) within ESA’s General Support Technology Program (GSTP) for the preliminary GR765 system requirement development.

“ESA is proud to collaborate with CAES in developing this next generation of data processing technology which is instrumental to build intelligent, powerful and secure systems in space. Our cooperation will enhance Europe’s capacity to launch and conduct its ambitious future missions and puts us in a pole position to advance the global technological standard for data processing in space,” said Elodie Viau, Director of Telecommunications and Integrated Applications at ESA.

“The CAES GR765 responds to the ever-increasing demands of telecommunication payload data processing, but also benefits a broad range of other mission-critical applications such as on-board computing,” said Michael Harverson, Head of the Space Segment Section at ESA.

ESA’s ARTES (Advanced Research in Telecommunications Systems) program is unique in Europe and aims to support the competitiveness of European and Canadian industry for the platform or payload of a satellite, a user terminal, or a full telecom system integrating a network with its space segment.;

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