Standalone controller IP for the Controller Area Network
New Products
|
By
eeNews Europe
The DCAN supports both standard (11 bit identifier) and extended (29 bit identifier) frames and data rates up to 1 Mbps. Hardware message filtering and 64 byte receive FIFO enables back-to-back message reception with minimum CPU load. The DCAN is described at RTL level allowing target use in FPGA or ASIC technologies. The IP is fully synthesizable and comes as a static synchronous design with positive edge clocking and synchronous reset. It is delivered scan-test ready, with VHDL source code or VERILOG source code, encrypted or in plain text EDIF netlist, with documentation, IP core updates and technical support.
Get the data sheet
Visit Digital Core Design at www.dcd.pl
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
eeNews on Google News