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Starchip to integrate Crocus magnetic logic into SoCs

Starchip to integrate Crocus magnetic logic into SoCs

Technology News |
By eeNews Europe



Crocus and Sophia-Antipolis-based Starchip will work together to embed the Crocus magnetic logic unit (MLU) memory and logic functionality into next generation secure processor-based architectures.

Crocus’ MLU, first announced in June 2011, is based on a new self-referencing magnetics architecture that is a scalable version of Crocus’ Thermally Assisted Switching (TAS) technology. This enables practical implementation of advanced magnetic logic and memory capabilities.

”This partnership with Starchip is an ideal solution for serving our customers seeking to integrate MLU technology into their advanced chip designs,” said Dr. Bertrand Cambou, executive chairman of Crocus Technology. “We are confident that the Starchip team’s well-established track record of successful implementation will enhance our ability to help our customers get to high-volume production quickly.”

“We believe that MLU will bring great value to our customers," said Lucien Brau, Starchip president and CEO. "Starchip’s strong know-how in embedded hardware security, combined with the new security features offered by Crocus’ MLU technology, will allow us to bring a very innovative, advanced and robust solution to the security market,”. “Starchip looks forward to extending Crocus’ embedded design reach to a large number of customers.”

Starchip raised €1.125m  last month to help develop its design business with a focus on mass production devices.

Crocus’ first generation magnetic technology was originally conceived at the Grenoble-based Spintec, a magnetic research laboratory affiliated with French labs CEA and CNRS. It was further developed for production at SVTC in California and is in its final phase of implementation on the 130nm process at Tower Jazz semiconductor. It has separate deals with IBM and RUSNANO, forming a joint venture, Crocus Nano Electronics (CNE), to build and operate a fab in Russia for magnetic semiconductors at the 90nm, 65nm and 45nm process nodes.

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