Startup aims many-core chip at smartphones
Olofsson’s 2007 epiphany became his 2011 many-core Epiphany chip, an accelerator for next-generation DSP tasks such as speech recognition and imaging processing. The current implementation packs 16 custom floating-point cores in a 65nm chip that deliver 50 GFLOPS consuming less than a watt.
"I was here going to presentations, and it clicked that something was missing," said Olofsson in an interview at ESC.
In ten years at ADI, he had worked both on large teams that spent $100 million creating high-end DSPs that failed to get adequate market traction and virtually alone on simple microcontroller designs. He had also tracked middle-of-the-road DSPs based on SIMD and VLIW architectures that could not scale beyond eight-way devices.
Multicore mania was in the air that year at ESC. It struck the ADI engineer that he could develop a custom floating point core and hook many of them up in an architecture that would attack the high end DSP space without running up a $100 million development tab.
Olofsson cashed out his retirement account and started work. Eighteen months ago he had a prototype that looked good enough to win him funding from DSP board maker BittWare Inc.
He hired two engineers and turned the crank on the design. "Boy, it’s been tough in the last year and a half bringing that prototype to the level of a product," he said.
But he did, and this week BittWare is expected to announce its first of several systems customers, initially focusing on imaging processing for radar. The next step is even bigger: Olofsson hopes to snag a tier-one silicon company willing to take his architecture to market for next-generation mobile systems.
Epiphany can scale to more than a thousand cores opening up use in base stations and high-performance computers significantly smaller than today’s systems. "But there’s not as much impetus to go for revolutionary performance there as in drones and smartphones where you don’t have a product unless you are energy efficient," he said.
Avoiding a startup graveyard
Silicon Valley is littered with failed startups from Ambric to Quicksilver who had visions of massively parallel processors running next-generation apps. The novel architectures often proved difficult to program, the next-gen apps failed to materialize and funding dried up.
Olofsson has studied their history and hopes to avoid their faults. Unlike the earlier startups, Adapteva is not trying to unseat existing dual- and quad core host processors, but open up new sockets for high end DSP arrays.
"What we think is missing is a general-purpose accelerator—not for baseband or graphics jobs that are being handled quite well–but for things like speech or face recognition or real-time imaging processing," Olofsson said.
He shakes off the notion that such apps for all practical purposes don’t exist in today’s smartphone market. "There’s no such thing as too much performance, and ten years from now who knows what the smartphone will look like," he asks.
Silicon vendors might even be interested in Epiphany for its many-core architecture based on a mesh network of nodes, each with its own core and memory. The architecture uses a flat memory model where cores can run independently or address any other core’s memory.
The approach means developers can program the chip in C with existing tools like the GNU GCC compiler. That was one of the attractions for BittWare that sold FPGA accelerator boards, but they could not be programmed in C.
Adapteva has a debugger, IDE front end and runtime libraries available with a developer’s kit, but it has a few months of work ahead on higher level software support. For instance, it is developing a message passing framework based on a standard from the Multicore Association.
To keep his four-person company lean, Olofsson is reaching out to an unnamed software partner for help creating the higher level tools. The partner will be announced in about a month.
"A lot of people do it all themselves, and just like that they spend $75 million," he said.
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