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Startup aims to simplify networks with programmable switch chip

Startup aims to simplify networks with programmable switch chip

Technology News |
By Jean-Pierre Joosting



Izzard is chief executive of Barefoot Networks, a rare microprocessor startup that has attracted a whopping $130 million in funding to date including strategic backers that include Google, Goldman Sachs and Hewlett-Packard Enterprise. Its Tofino chips aim to make the job of programming complex networks as easy as writing C++ code in an emerging open-source language it helped create called P4.

Barefoot is at the bleeding edge of a trend generally called software-defined networking. SDN represents an effort to cut through what’s become a rat’s nest of competing, often proprietary APIs, protocols and ASICs.

The chips and software are embedded in systems from giants such as Cisco, Ericsson, Huawei, Juniper and Nokia. SDN proponents aim to run much of the work of these systems on standard computer servers controlled by programs written in high-level languages.

Managing networks through servers is hard enough. But this so-called control plane is not nearly as complex and fast moving as the data plane where bits need to get switched and routed on the fly at speeds from 10-100 Gbits/second. This is the area where Barefoot hopes its chips and P4 will play.

“We think this is a unique idea and the financial markets in Silicon Valley have validated it,” said Izzard. With partners such as Google, Goldman, HPE and other unnamed OEMs, “we have big potential customers who can ramp fast” for large Web-scale data centers and enterprise users, said Izzard who used to help big networking OEMs develop their ASICs while working at Texas Instruments.


Barefoot closed its latest round for $57 million a few weeks ago. It expects to sample chips before the end of the year to multiple customers some of whom are already starting system designs. “We can see ourselves in production in mid-2017 and have money to get beyond that and plenty of customer interest to serve,” he said.

Analyst Bob Wheeler of The Linley Group is upbeat on the new P4 language Barefoot helped create, but says the startup now has to prove its chip technology.

“I view P4 as delivering on what OpenFlow should have been — OpenFlow was supposed to deliver highly-configurable pipelines, but instead it was constrained by legacy protocols and silicon,” Wheeler said.

“P4 takes a clean-sheet approach, creating an SDN data plane with room to grow,” said Wheeler. “How quickly the market takes off will depend on hyper-scale operators like Amazon, Facebook, Google, and Microsoft,” he added.

In a press release officially announcing the startup, senior managers from China’s Huawei and Tencent and others praised the Barefoot concept.

“One of the key components of LinkedIn’s next-generation data center design is a programmable network fabric and we are excited about the opportunities Tofino and P4 enable to be one of the building blocks in our vision,” said Yuval Bachar, a principal engineer at LinkedIn, which Microsoft recently bid to acquire.


The status of the P4 effort provides a glimpse of how Barefoot’s chip and the overall SDN effort is doing.

Nick McKeown, a Stanford professor and co-founder and chief scientist at Barefoot, helped launch P4. A spec for the language was published a little more than three years ago and about 100 people attended a recent P4 workshop including representatives of AT&T, Facebook, Intel, Microsoft, Netronome and Xilinx.

Earlier this year, AT&T said it created a proof of concept with P4 on systems from Juniper in 30 days using just 78 lines of code. Service providers Comcast and Korea’s two main telecom providers are among the more than 40 members of the P4 group.

Netronome, which acquired Intel’s IXP network processor, is among the more bullish supporters of the software. It demoed a developer’s kit about to go into production for running P4 on its network-interface cards, although the P4 group is still evolving its compiler spec.

“The feature set is good enough for people to build production solutions…I expect we could see some P4 deployments next year,” said Sujal Das, a general manager of data center strategy at Netronome. “We have three users who are large operators and cloud service providers who have our hardware and tools working on early proof-of-concepts with P4, and three large OEMs developing data planes using our tools,” he said.

The P4 group has gained 40 backers since it was launched three years ago (Image: Netronome).

To bolster its effort, Netronome recently launched a lab dedicated to work on accelerating server-based SDN as well as a series of webinars on the topic.


The Open Network Function Processing lab is “a place for work on data plane acceleration that started as a Netronome project for data plane acceleration research, but we hope to invite other hardware accelerator makers to join us,” said Bapi Vinnakota, a director of technology and alliances at Netronome who runs the lab.

Among other P4 members, Xilinx has showed the software running on its FPGAs, and Intel demoed it on networking cards. Huawei is believed to be planning to run P4 on its own silicon.

One quiet giant in the room is Broadcom. Its merchant switch chips are used widely, especially in data center switches. Broadcom joined the P4 group but has not announced any plans for chips supporting it. Cavium also is a member with no announced plans to date.

The Tofino chip has a pipeline dedicated to performing matches and actions for every 16 Ethernet MACs (Image: Barefoot).

Barefoot’s high-end Tofino chip can accommodate flexible configurations of up to 64 100Gbit Ethernet media access controllers or more, slower MACs. It handles all routing functions through Layer 4, assigning one pipeline to every 16 MACs.

In general, SDN processors quickly read packet headers and take actions on them. The chips are “dominated by I/O and memory with a single shared memory buffer and a set of pipelines, so they are very uniform,” said Izzard.


The startup won’t describe just what’s inside the pipelines in terms of look-up tables, packet processors and traffic managers, nor will it give size, power consumption or cost figures for the chip. However it did say it is on par with existing merchant chips. Thus Barefoot’s low-end chip, which handles 32 MACs, should roughly compare to Broadcom’s Tomahawk switch, released in September 2014.

The Tofino chips use both SRAM and TCAM memories. They are made in a 16nm process and can be cooled with standard heat sinks and fans.

“There’s no price premium for our level of programmability, which makes it easy to choose this device,” said Ed Doe, who heads up product marketing for Barefoot.

Barefoot designed two systems to demonstrate the chip—one using the 64-port chip in a 2U top-of rack switch with 65 QSFP ports and a 1U system using the 32-port chip.

Some of Barefoot’s secret sauce is embedded in its P4 compiler, called Capilano. In a sign of the importance of the code, about half the startup’s staff are software engineers.

The team also mixes veterans from traditional network switch makers such as Broadcom, Cisco and Juniper with young engineers recruited by co-founder McKeown from Stanford and elsewhere.

“We managed to mix people with experience and a lot of fresh talent from academia with a clean-slate view of the world,” said Doe. “When you challenge the standard way things are done, you have to have that mix,” he said.

Izzard and McKeown have worked on various projects for 25 years including startup Abrizio which designed a Tbit switch fabric. Both were involved in SDN from the early days when data center giants such as Google started pushing for simpler ways to manage their networks of thousands of servers.

“We thought about building a programmable data forwarding platform that would do for networking what Nvidia did for graphics,” said Izzard. “Switching is a match/action process, and the network workload is very parallel with very little serial dependence, so we set out to build a protocol-independent switch,” he said.

By Rick Merritt, Silicon Valley Bureau Chief, EE Times

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